docs: Update 17.3.0 release notes

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

.travis.yml

@@ -30,40 +30,6 @@ env:
 
 matrix:
   include:
-    - env:
-        - LABEL="meson Vulkan"
-        - BUILD=meson
-        - MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers="
-        - LLVM_VERSION=4.0
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-      addons:
-        apt:
-          sources:
-            - llvm-toolchain-trusty-4.0
-          packages:
-            # LLVM packaging is broken and misses these dependencies
-            - libedit-dev
-            # From sources above
-            - llvm-4.0-dev
-            # Common
-            - xz-utils
-            - libexpat1-dev
-            - libelf-dev
-            - python3-pip
-    - env:
-        - LABEL="meson loaders/classic DRI"
-        - BUILD=meson
-        - MESON_OPTIONS="-Dvulkan-drivers= -Dgallium-drivers="
-      addons:
-        apt:
-          packages:
-            - xz-utils
-            - x11proto-xf86vidmode-dev
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libxdamage-dev
-            - libxfixes-dev
-            - python3-pip
     - env:
         - LABEL="make loaders/classic DRI"
         - BUILD=make
@@ -399,44 +365,45 @@ matrix:
             - libx11-xcb-dev
             - libelf-dev
     - env:
-        - LABEL="macOS make"
-        - BUILD=make
-        - MAKEFLAGS="-j4"
-        - MAKE_CHECK_COMMAND="make check"
-        - DRI_LOADERS="--with-platforms=x11 --disable-egl"
-      os: osx
-
-before_install:
-  - |
-    if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
-      HOMEBREW_NO_AUTO_UPDATE=1 brew install python3 ninja expat gettext
-      # Set PATH for homebrew pip3 installs
-      PATH="$HOME/Library/Python/3.6/bin:${PATH}"
-      # Set PKG_CONFIG_PATH for keg-only expat
-      PKG_CONFIG_PATH="/usr/local/opt/expat/lib/pkgconfig:${PKG_CONFIG_PATH}"
-      # Set PATH for keg-only gettext
-      PATH="/usr/local/opt/gettext/bin:${PATH}"
-
-      # Install xquartz for prereqs ...
-      XQUARTZ_VERSION="2.7.11"
-      wget -nv https://dl.bintray.com/xquartz/downloads/XQuartz-${XQUARTZ_VERSION}.dmg
-      hdiutil attach XQuartz-${XQUARTZ_VERSION}.dmg
-      sudo installer -pkg /Volumes/XQuartz-${XQUARTZ_VERSION}/XQuartz.pkg -target /
-      hdiutil detach /Volumes/XQuartz-${XQUARTZ_VERSION}
-      # ... and set paths
-      PATH="/opt/X11/bin:${PATH}"
-      PKG_CONFIG_PATH="/opt/X11/share/pkgconfig:/opt/X11/lib/pkgconfig:${PKG_CONFIG_PATH}"
-      ACLOCAL="aclocal -I /opt/X11/share/aclocal -I /usr/local/share/aclocal"
-    fi
+        - LABEL="meson Vulkan"
+        - BUILD=meson
+        - MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers="
+      addons:
+        apt:
+          sources:
+            - llvm-toolchain-trusty-3.9
+          packages:
+            # LLVM packaging is broken and misses these dependencies
+            - libedit-dev
+            # From sources above
+            - llvm-3.9-dev
+            # Common
+            - xz-utils
+            - libexpat1-dev
+            - libelf-dev
+            - python3-pip
+    - env:
+        - LABEL="meson loaders/classic DRI"
+        - BUILD=meson
+        - MESON_OPTIONS="-Dvulkan-drivers= -Dgallium-drivers="
+      addons:
+        apt:
+          packages:
+            - xz-utils
+            - x11proto-xf86vidmode-dev
+            - libexpat1-dev
+            - libx11-xcb-dev
+            - libxdamage-dev
+            - libxfixes-dev
+            - python3-pip
 
 install:
-  - pip2 install --user mako
+  - pip install --user mako
 
-  # Install a more modern meson from pip, since the version in the
-  # ubuntu repos is often quite old. Avoid >=0.45.0 as it needs python
-  # 3.5+
+  # Install the latest meson from pip, since the version in the ubuntu repos is
+  # often quite old.
   - if test "x$BUILD" = xmeson; then
-      pip3 install --user "meson<0.45.0";
+      pip3 install --user meson;
     fi
 
   # Since libdrm gets updated in configure.ac regularly, try to pick up the
@@ -452,64 +419,62 @@ install:
   # Install dependencies where we require specific versions (or where
   # disallowed by Travis CI's package whitelisting).
 
-  - |
-    if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then
-      wget $XORG_RELEASES/util/$XORGMACROS_VERSION.tar.bz2
-      tar -jxvf $XORGMACROS_VERSION.tar.bz2
-      (cd $XORGMACROS_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget $XORG_RELEASES/util/$XORGMACROS_VERSION.tar.bz2
+  - tar -jxvf $XORGMACROS_VERSION.tar.bz2
+  - (cd $XORGMACROS_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      wget $XORG_RELEASES/proto/$GLPROTO_VERSION.tar.bz2
-      tar -jxvf $GLPROTO_VERSION.tar.bz2
-      (cd $GLPROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget $XORG_RELEASES/proto/$GLPROTO_VERSION.tar.bz2
+  - tar -jxvf $GLPROTO_VERSION.tar.bz2
+  - (cd $GLPROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      wget $XORG_RELEASES/proto/$DRI2PROTO_VERSION.tar.bz2
-      tar -jxvf $DRI2PROTO_VERSION.tar.bz2
-      (cd $DRI2PROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget $XORG_RELEASES/proto/$DRI2PROTO_VERSION.tar.bz2
+  - tar -jxvf $DRI2PROTO_VERSION.tar.bz2
+  - (cd $DRI2PROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      wget $XCB_RELEASES/$XCBPROTO_VERSION.tar.bz2
-      tar -jxvf $XCBPROTO_VERSION.tar.bz2
-      (cd $XCBPROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget $XCB_RELEASES/$XCBPROTO_VERSION.tar.bz2
+  - tar -jxvf $XCBPROTO_VERSION.tar.bz2
+  - (cd $XCBPROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      wget $XCB_RELEASES/$LIBXCB_VERSION.tar.bz2
-      tar -jxvf $LIBXCB_VERSION.tar.bz2
-      (cd $LIBXCB_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget $XCB_RELEASES/$LIBXCB_VERSION.tar.bz2
+  - tar -jxvf $LIBXCB_VERSION.tar.bz2
+  - (cd $LIBXCB_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      wget $XORG_RELEASES/lib/$LIBPCIACCESS_VERSION.tar.bz2
-      tar -jxvf $LIBPCIACCESS_VERSION.tar.bz2
-      (cd $LIBPCIACCESS_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget $XORG_RELEASES/lib/$LIBPCIACCESS_VERSION.tar.bz2
+  - tar -jxvf $LIBPCIACCESS_VERSION.tar.bz2
+  - (cd $LIBPCIACCESS_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      wget http://dri.freedesktop.org/libdrm/$LIBDRM_VERSION.tar.bz2
-      tar -jxvf $LIBDRM_VERSION.tar.bz2
-      (cd $LIBDRM_VERSION && ./configure --prefix=$HOME/prefix --enable-vc4 --enable-freedreno --enable-etnaviv-experimental-api && make install)
+  - wget http://dri.freedesktop.org/libdrm/$LIBDRM_VERSION.tar.bz2
+  - tar -jxvf $LIBDRM_VERSION.tar.bz2
+  - (cd $LIBDRM_VERSION && ./configure --prefix=$HOME/prefix --enable-vc4 --enable-freedreno --enable-etnaviv-experimental-api && make install)
 
-      wget $XORG_RELEASES/lib/$LIBXSHMFENCE_VERSION.tar.bz2
-      tar -jxvf $LIBXSHMFENCE_VERSION.tar.bz2
-      (cd $LIBXSHMFENCE_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget $XORG_RELEASES/lib/$LIBXSHMFENCE_VERSION.tar.bz2
+  - tar -jxvf $LIBXSHMFENCE_VERSION.tar.bz2
+  - (cd $LIBXSHMFENCE_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      wget http://people.freedesktop.org/~aplattner/vdpau/$LIBVDPAU_VERSION.tar.bz2
-      tar -jxvf $LIBVDPAU_VERSION.tar.bz2
-      (cd $LIBVDPAU_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget http://people.freedesktop.org/~aplattner/vdpau/$LIBVDPAU_VERSION.tar.bz2
+  - tar -jxvf $LIBVDPAU_VERSION.tar.bz2
+  - (cd $LIBVDPAU_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      wget http://www.freedesktop.org/software/vaapi/releases/libva/$LIBVA_VERSION.tar.bz2
-      tar -jxvf $LIBVA_VERSION.tar.bz2
-      (cd $LIBVA_VERSION && ./configure --prefix=$HOME/prefix --disable-wayland --disable-dummy-driver && make install)
+  - wget http://www.freedesktop.org/software/vaapi/releases/libva/$LIBVA_VERSION.tar.bz2
+  - tar -jxvf $LIBVA_VERSION.tar.bz2
+  - (cd $LIBVA_VERSION && ./configure --prefix=$HOME/prefix --disable-wayland --disable-dummy-driver && make install)
 
-      wget $WAYLAND_RELEASES/$LIBWAYLAND_VERSION.tar.xz
-      tar -axvf $LIBWAYLAND_VERSION.tar.xz
-      (cd $LIBWAYLAND_VERSION && ./configure --prefix=$HOME/prefix --enable-libraries --without-host-scanner --disable-documentation --disable-dtd-validation && make install)
+  - wget $WAYLAND_RELEASES/$LIBWAYLAND_VERSION.tar.xz
+  - tar -axvf $LIBWAYLAND_VERSION.tar.xz
+  - (cd $LIBWAYLAND_VERSION && ./configure --prefix=$HOME/prefix --enable-libraries --without-host-scanner --disable-documentation --disable-dtd-validation && make install)
 
-      wget $WAYLAND_RELEASES/$WAYLAND_PROTOCOLS_VERSION.tar.xz
-      tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
-      (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && make install)
+  - wget $WAYLAND_RELEASES/$WAYLAND_PROTOCOLS_VERSION.tar.xz
+  - tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
+  - (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      # Meson requires ninja >= 1.6, but trusty has 1.3.x
-      wget https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip
-      unzip ninja-linux.zip
-      mv ninja $HOME/prefix/bin/
+  # Meson requires ninja >= 1.6, but trusty has 1.3.x
+  - wget https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip;
+  - unzip ninja-linux.zip
+  - mv ninja $HOME/prefix/bin/
 
-      # Generate this header since one is missing on the Travis instance
-      mkdir -p linux
-      printf "%s\n" \
+  # Generate the header since one is missing on the Travis instance
+  - mkdir -p linux
+  - printf "%s\n" \
            "#ifndef _LINUX_MEMFD_H" \
            "#define _LINUX_MEMFD_H" \
            "" \
@@ -520,7 +485,6 @@ install:
            "#define MFD_ALLOW_SEALING       0x0002U" \
            "" \
            "#endif /* _LINUX_MEMFD_H */" > linux/memfd.h
-    fi
 
 script:
   - if test "x$BUILD" = xmake; then
@@ -548,28 +512,8 @@ script:
       scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
     fi
 
-  - |
-    if test "x$BUILD" = xmeson; then
-
-      # Travis CI has moved to LLVM 5.0, and meson is detecting
-      # automatically the available version in /usr/local/bin based on
-      # the PATH env variable order preference.
-      #
-      # As for 0.44.x, Meson cannot receive the path to the
-      # llvm-config binary as a configuration parameter. See
-      # https://github.com/mesonbuild/meson/issues/2887 and
-      # https://github.com/dcbaker/meson/commit/7c8b6ee3fa42f43c9ac7dcacc61a77eca3f1bcef
-      #
-      # We want to use the custom (APT) installed version. Therefore,
-      # let's make Meson find our wanted version sooner than the one
-      # at /usr/local/bin
-      #
-      # Once this is corrected, we would still need a patch similar
-      # to:
-      # https://lists.freedesktop.org/archives/mesa-dev/2017-December/180217.html
-      test -f /usr/bin/$LLVM_CONFIG && ln -s /usr/bin/$LLVM_CONFIG $HOME/prefix/bin/llvm-config
-
-      export CFLAGS="$CFLAGS -isystem`pwd`"
-      meson _build $MESON_OPTIONS
-      ninja -C _build
+  - if test "x$BUILD" = xmeson; then
+      export CFLAGS="$CFLAGS -isystem`pwd`";
+      meson _build $MESON_OPTIONS;
+      ninja -C _build;
     fi

Android.common.mk

@@ -31,7 +31,6 @@ LOCAL_C_INCLUDES += \
 
 MESA_VERSION := $(shell cat $(MESA_TOP)/VERSION)
 LOCAL_CFLAGS += \
-	-Wno-error \
 	-Wno-unused-parameter \
 	-Wno-pointer-arith \
 	-Wno-missing-field-initializers \
@@ -57,9 +56,6 @@ LOCAL_CFLAGS += \
 	-DHAVE_FUNC_ATTRIBUTE_FORMAT \
 	-DHAVE_FUNC_ATTRIBUTE_PACKED \
 	-DHAVE_FUNC_ATTRIBUTE_ALIAS \
-	-DHAVE_FUNC_ATTRIBUTE_NORETURN \
-	-DHAVE_FUNC_ATTRIBUTE_RETURNS_NONNULL \
-	-DHAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT \
 	-DHAVE___BUILTIN_CTZ \
 	-DHAVE___BUILTIN_POPCOUNT \
 	-DHAVE___BUILTIN_POPCOUNTLL \
@@ -69,9 +65,6 @@ LOCAL_CFLAGS += \
 	-DHAVE_PTHREAD=1 \
 	-DHAVE_DLADDR \
 	-DHAVE_DL_ITERATE_PHDR \
-	-DHAVE_LINUX_FUTEX_H \
-	-DHAVE_ENDIAN_H \
-	-DHAVE_ZLIB \
 	-DMAJOR_IN_SYSMACROS \
 	-fvisibility=hidden \
 	-Wno-sign-compare

Android.mk

@@ -39,7 +39,6 @@ endif
 MESA_DRI_MODULE_REL_PATH := dri
 MESA_DRI_MODULE_PATH := $(TARGET_OUT_SHARED_LIBRARIES)/$(MESA_DRI_MODULE_REL_PATH)
 MESA_DRI_MODULE_UNSTRIPPED_PATH := $(TARGET_OUT_SHARED_LIBRARIES_UNSTRIPPED)/$(MESA_DRI_MODULE_REL_PATH)
-MESA_DRI_LDFLAGS := -Wl,--build-id=sha1
 
 MESA_COMMON_MK := $(MESA_TOP)/Android.common.mk
 MESA_PYTHON2 := python

Makefile.am

@@ -35,7 +35,6 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
 	--enable-glx-tls \
 	--enable-nine \
 	--enable-opencl \
-	--enable-opencl-icd \
 	--enable-opengl \
 	--enable-va \
 	--enable-vdpau \
@@ -59,13 +58,7 @@ EXTRA_DIST = \
 	scons \
 	SConstruct \
 	build-support/conftest.dyn \
-	build-support/conftest.map \
-	meson.build \
-	meson_options.txt \
-	bin/meson.build \
-	include/meson.build \
-	bin/install_megadrivers.py \
-	bin/meson_get_version.py
+	build-support/conftest.map
 
 noinst_HEADERS = \
 	include/c99_alloca.h \

REVIEWERS

@@ -74,15 +74,6 @@ EGL
 R: Eric Engestrom <eric@engestrom.ch>
 F: src/egl/
 
-HAIKU
-R: Alexander von Gluck IV <kallisti5@unixzen.com>
-F: include/HaikuGL/
-F: src/egl/drivers/haiku/
-F: src/gallium/state_trackers/hgl/
-F: src/gallium/targets/haiku-softpipe/
-F: src/gallium/winsys/sw/hgl/
-F: src/hgl/
-
 GALLIUM LOADER
 R: Emil Velikov <emil.l.velikov@gmail.com>
 F: src/gallium/auxiliary/pipe-loader/

VERSION

@@ -1 +1 @@
-18.0.5
+17.3.0

bin/.cherry-ignore

@@ -1,90 +0,0 @@
-# fixes: The following commits were applied without the "cherry-picked from" tag
-50265cd9ee4caffee853700bdcd75b92eedc0e7b automake: anv: ship anv_extensions_gen.py in the tarball
-ac4437b20b87c7285b89466f05b51518ae616873 automake: small cleanup after the meson.build inclusion
-
-# stable: The KHX extension is disabled all together in the stable branches.
-2ffe395cba0f7b3c1f1c41062f4376eae3a188b5 radv: Don't expose VK_KHX_multiview on android.
-
-# stable: There is a specific version for this patch for stable branches, but
-#         it is causing regressions.
-85d0bec9616bc1ffa8e4ab5e7c5d12ff4e414872 anv: Be more careful about fast-clear colors
-
-# fixes: The commit fixes earlier commit 1c57a6da5e3 which did not land in
-#        branch.
-3401b028df1074a06a7fbc3fb1cda949646ef75d ac/shader: fix vertex input with components.
-
-# fixes: The commit requires earlier commits 639c4f2b54a6 and 2cfba40eea4c
-#        which did not land in branch.
-8f052a3e257a61240cb311032497d016278117a8 radv: handle exporting view index to fragment shader. (v1.1)
-
-# fixes: The commit fixes earlier commits 83d4a5d5aea5a8a05be2,
-#        b2f2236dc565dd1460f0 and c62cf1f165919bc74296 which did not land in
-#        branch.
-880c1718b6d14b33fe5ba918af70fea5be890c6b omx: always define ENABLE_ST_OMX_{BELLAGIO,TIZONIA}
-
-# stable: There is a specific port for this patch for stable branch.
-d15fb766aa3c98ffbe16d050b2af4804e4b12c57 radeonsi/gfx9: fix a hang with an empty first IB
-
-# stable: Explicit 18.1 only nominations
-0e945fdf23bac5a62c15edfcbfd9d6ac4eee592f nir: Do not use progress for unreachable code in return lowering.
-84fef802fb16cef68ec358cbfed1cac9c3bfa410 ac/nir: add missing round_slice for 1D arrays
-d136a5fad9c7e67c1362453388914ecc60420883 ac: fix the number of coordinates for ac_image_get_lod and arrays
-
-# stable: There is a specific port for this patch for stable branch.
-fedd0a4215bcd387525000d76b77993ca38916ae radv/winsys: allow to submit up to 4 IBs for chips without chaining
-
-# stable: Explicit 18.1 only nominations
-413c5ca3727898fdb4fa1d2849d0c2defdd77b48 travis: update libva required version
-a6fbefa67b5b0ed1ee42a9034ee74dfaed1c389a radv: fix DCC enablement since partial MSAA implementation
-d7ffe3b384f4d1c15a9364768cf405d416522e60 radv: set ac_surf_info::num_channels correctly
-d38425ce872c4a00cfb691ae9dceca6a07afc516 ac: fix texture query LOD for 1D textures on GFX9
-4d449c94e450c33d7b2b09c1c263322042503893 autotools, meson: bump up required VA version
-
-# stable: Explicit 18.1 only nominations
-9267ff9883f749dd1708c573c0df4b46687ff973 radv: Allow vkEnumerateInstanceVersion ProcAddr without instance.
-467c562a292b4424f24381932b90bcb9869c3d73 radv: Don't check the incoming apiVersion on CreateInstance.
-b17cfb08a3fc9a599eff64fffe48daba398a672f vulkan/wsi: Only use LINEAR modifier for prime if supported.
-597b9e881083533b987dbcbb8f679ca1eefff974 radeonsi/gfx9: work around a GPU hang due to broken indirect indexing in LLVM
-62f50df7b79c273a0eb9bf769eded76933bddc3a radv: Fix multiview queries.
-
-# stable: The commit requires earlier commit ba79a90fb52 which did not land in
-#         branch.
-901db25d5b7cd2ac2dd648b370c4bddf23dd5c44 glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug
-
-# stable: The commit fixes earlier commit d5f42f96e16 which did not land in
-#         branch.
-d07466fe18522cde1acadfc597583f80b69c15b7 mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs
-
-# stable: The commit fixes earlier commit d07466fe18522 which did not land in
-#         branch.
-e4211b36bba4acde3e56ce1e22b12759e820a241 mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT
-
-# stable: The commit requires earlier commits ab0e625a671 and 62510846b6e which
-#         did not land in branch.
-b16fc6cda11576a4dd6c8d95f7bee94121c4b8e7 radv/resolve: do fmask decompress on all layers.
-
-# stable: There is a specific port for this patch for stable branch.
-3d4d388e3929d7948b62d90867357aecbfba5aeb radv: Fix up 2_10_10_10 alpha sign.
-
-# stable: The commit requires earlier commit af4e9295fe which did not land in
-#         branch.
-816f2dc67da72be8993e724aeda4c2ec2f5a2978 i965/miptree: Fix handling of uninitialized MCS buffers
-
-# stable: Explicit 18.1 only nominations
-549e54270ba3a519b46a1fbffa4aa6b628a052d3 radv: fix VK_EXT_descriptor_indexing
-
-# fixes: The commit fixes earlier commits 19a91841c3 and 9987a072cb which did
-#        not land in branch.
-d89f58a6b8436b59dcf3b896c0ccddabed3f78fd mesa/st: handle vert_attrib_mask in nir case too
-
-# stable: Tegra support is not part of the current branch
-bd3e97e5aad7800b8e17ed10d34a070926691945 tegra: Remove usage of non-stable UAPI
-9603d81df05105857b676f20dff964ef3ab0ecff tegra: Fix scanout resources without modifiers
-9e539012dfaa848fc4cfde83c3f3a83fee274ca4 tegra: Treat resources with modifiers as scanout
-
-# stable: The commit requires earlier commit 19a91841c3 which did not land in
-#         branch.
-a7d0c53ab89ca86b705014925214101f5bc4187f st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)
-
-# stable: Explicit 18.1 only nomination
-30918b77ac82ba1da7764c0375233656e0ebf9f9 nv30: ensure that displayable formats are marked accordingly

bin/git_sha1_gen.py

@@ -6,7 +6,6 @@ The output of this script goes to stdout.
 """
 
 
-import argparse
 import os
 import os.path
 import subprocess
@@ -28,22 +27,10 @@ def get_git_sha1():
         git_sha1 = ''
     return git_sha1
 
-parser = argparse.ArgumentParser()
-parser.add_argument('--output', help='File to write the #define in',
-        required=True)
-args = parser.parse_args()
 
 git_sha1 = os.environ.get('MESA_GIT_SHA1_OVERRIDE', get_git_sha1())[:10]
 if git_sha1:
     git_sha1_h_in_path = os.path.join(os.path.dirname(sys.argv[0]),
             '..', 'src', 'git_sha1.h.in')
     with open(git_sha1_h_in_path , 'r') as git_sha1_h_in:
-        new_sha1 = git_sha1_h_in.read().replace('@VCS_TAG@', git_sha1)
-        if os.path.isfile(args.output):
-            with open(args.output, 'r') as git_sha1_h:
-                if git_sha1_h.read() == new_sha1:
-                    quit()
-        with open(args.output, 'w') as git_sha1_h:
-            git_sha1_h.write(new_sha1)
-else:
-    open(args.output, 'w').close()
+        sys.stdout.write(git_sha1_h_in.read().replace('@VCS_TAG@', git_sha1))

bin/install_megadrivers.py

@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 # encoding=utf-8
-# Copyright © 2017-2018 Intel Corporation
+# Copyright © 2017 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
@@ -35,11 +35,7 @@ def main():
     parser.add_argument('drivers', nargs='+')
     args = parser.parse_args()
 
-    if os.path.isabs(args.libdir):
-        to = os.path.join(os.environ.get('DESTDIR', '/'), args.libdir[1:])
-    else:
-        to = os.path.join(os.environ['MESON_INSTALL_DESTDIR_PREFIX'], args.libdir)
-
+    to = os.path.join(os.environ.get('MESON_INSTALL_DESTDIR_PREFIX'), args.libdir)
     master = os.path.join(to, os.path.basename(args.megadriver))
 
     if not os.path.exists(to):
@@ -48,24 +44,10 @@ def main():
 
     for each in args.drivers:
         driver = os.path.join(to, each)
-
         if os.path.exists(driver):
             os.unlink(driver)
-        print('installing {} to {}'.format(args.megadriver, driver))
+        print('installing {} to {}'.format(args.megadriver, to))
         os.link(master, driver)
-
-        try:
-            ret = os.getcwd()
-            os.chdir(to)
-
-            name, ext = os.path.splitext(each)
-            while ext != '.so':
-                if os.path.exists(name):
-                    os.unlink(name)
-                os.symlink(each, name)
-                name, ext = os.path.splitext(name)
-        finally:
-            os.chdir(ret)
     os.unlink(master)
 
 

bin/meson.build

@@ -1,21 +0,0 @@
-# Copyright © 2017 Eric Engestrom
-
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-
-git_sha1_gen_py = files('git_sha1_gen.py')

bin/meson_get_version.py

@@ -1,35 +0,0 @@
-#!/usr/bin/env python
-# encoding=utf-8
-# Copyright © 2017 Intel Corporation
-
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-
-from __future__ import print_function
-import os
-
-
-def main():
-    filename = os.path.join(os.environ['MESON_SOURCE_ROOT'], 'VERSION')
-    with open(filename) as f:
-        version = f.read().strip()
-    print(version, end='')
-
-
-if __name__ == '__main__':
-    main()

configure.ac

@@ -74,11 +74,11 @@ AC_SUBST([OPENCL_VERSION])
 # in the first entry.
 LIBDRM_REQUIRED=2.4.75
 LIBDRM_RADEON_REQUIRED=2.4.71
-LIBDRM_AMDGPU_REQUIRED=2.4.89
+LIBDRM_AMDGPU_REQUIRED=2.4.85
 LIBDRM_INTEL_REQUIRED=2.4.75
 LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
-LIBDRM_FREEDRENO_REQUIRED=2.4.89
+LIBDRM_FREEDRENO_REQUIRED=2.4.74
 LIBDRM_ETNAVIV_REQUIRED=2.4.82
 
 dnl Versions for external dependencies
@@ -111,10 +111,6 @@ dnl Check for progs
 AC_PROG_CPP
 AC_PROG_CC
 AC_PROG_CXX
-dnl add this here, so the help for this environmnet variable is close to
-dnl other CC/CXX flags related help
-AC_ARG_VAR([CXX11_CXXFLAGS], [Compiler flag to enable C++11 support (only needed if not
-                              enabled by default and different  from -std=c++11)])
 AM_PROG_CC_C_O
 AM_PROG_AS
 AX_CHECK_GNU_MAKE
@@ -124,7 +120,6 @@ AC_PROG_MKDIR_P
 
 AC_SYS_LARGEFILE
 
-
 LT_PREREQ([2.2])
 LT_INIT([disable-static])
 
@@ -250,7 +245,6 @@ AX_GCC_FUNC_ATTRIBUTE([visibility])
 AX_GCC_FUNC_ATTRIBUTE([warn_unused_result])
 AX_GCC_FUNC_ATTRIBUTE([weak])
 AX_GCC_FUNC_ATTRIBUTE([alias])
-AX_GCC_FUNC_ATTRIBUTE([noreturn])
 
 AM_CONDITIONAL([GEN_ASM_OFFSETS], test "x$GEN_ASM_OFFSETS" = xyes)
 
@@ -315,11 +309,11 @@ AC_LANG_POP([C++])
 # - non-Linux/Posix OpenGL portions needs to build on MSVC 2013 (which
 #   supports most of C99)
 # - the rest has no compiler compiler restrictions
-AX_CHECK_COMPILE_FLAG([-Werror=pointer-arith],                 [MSVC2013_COMPAT_CFLAGS="$MSVC2013_COMPAT_CFLAGS -Werror=pointer-arith"])
-AX_CHECK_COMPILE_FLAG([-Werror=vla],                           [MSVC2013_COMPAT_CFLAGS="$MSVC2013_COMPAT_CFLAGS -Werror=vla"])
+AX_CHECK_COMPILE_FLAG([-Werror=pointer-arith],                 [MSVC2013_COMPAT_CFLAGS="-Werror=pointer-arith"])
+AX_CHECK_COMPILE_FLAG([-Werror=vla],                           [MSVC2013_COMPAT_CFLAGS="-Werror=vla"])
 AC_LANG_PUSH([C++])
-AX_CHECK_COMPILE_FLAG([-Werror=pointer-arith],                 [MSVC2013_COMPAT_CXXFLAGS="$MSVC2013_COMPAT_CXXFLAGS -Werror=pointer-arith"])
-AX_CHECK_COMPILE_FLAG([-Werror=vla],                           [MSVC2013_COMPAT_CXXFLAGS="$MSVC2013_COMPAT_CXXFLAGS -Werror=vla"])
+AX_CHECK_COMPILE_FLAG([-Werror=pointer-arith],                 [MSVC2013_COMPAT_CXXFLAGS="-Werror=pointer-arith"])
+AX_CHECK_COMPILE_FLAG([-Werror=vla],                           [MSVC2013_COMPAT_CXXFLAGS="-Werror=vla"])
 AC_LANG_POP([C++])
 
 AC_SUBST([MSVC2013_COMPAT_CFLAGS])
@@ -333,56 +327,6 @@ if test "x$GCC" = xyes; then
     fi
 fi
 
-dnl
-dnl Check whether C++11 is supported, if the environment variable
-dnl CXX11_CXXFLAGS is set it takes precedence.
-dnl
-
-AC_LANG_PUSH([C++])
-
-check_cxx11_available() {
-    output_support=$1
-    AC_COMPILE_IFELSE(
-        [AC_LANG_PROGRAM([
-             #if !(__cplusplus >= 201103L)
-             #error
-             #endif
-             #include <tuple>
-        ])
-    ], [
-         AC_MSG_RESULT(yes)
-         cxx11_support=yes
-    ], AC_MSG_RESULT(no))
-    eval "$output_support=\$cxx11_support"
-}
-
-HAVE_CXX11=no
-save_CXXFLAGS="$CXXFLAGS"
-
-dnl If the user provides a flag to enable c++11, then we test only this
-if test "x$CXX11_CXXFLAGS" != "x"; then
-   CXXFLAGS="$CXXFLAGS $CXX11_CXXFLAGS"
-   AC_MSG_CHECKING(whether c++11 is enabled by via $CXX11_CXXFLAGS)
-   check_cxx11_available HAVE_CXX11
-else
-   dnl test whether c++11 is enabled by default
-   AC_MSG_CHECKING(whether c++11 is enabled by default)
-   check_cxx11_available HAVE_CXX11
-
-   dnl C++11 not enabled by default, test whether -std=c++11 does the job
-   if test "x$HAVE_CXX11" != "xyes"; then
-       CXX11_CXXFLAGS=-std=c++11
-       CXXFLAGS="$CXXFLAGS $CXX11_CXXFLAGS"
-       AC_MSG_CHECKING(whether c++11 is enabled by via $CXX11_CXXFLAGS)
-       check_cxx11_available HAVE_CXX11
-   fi
-fi
-
-CXXFLAGS="$save_CXXFLAGS"
-AM_CONDITIONAL(HAVE_STD_CXX11, test "x$HAVE_CXX11" = "xyes")
-AC_SUBST(CXX11_CXXFLAGS)
-AC_LANG_POP([C++])
-
 dnl even if the compiler appears to support it, using visibility attributes isn't
 dnl going to do anything useful currently on cygwin apart from emit lots of warnings
 case "$host_os" in
@@ -395,10 +339,8 @@ esac
 AC_SUBST([VISIBILITY_CFLAGS])
 AC_SUBST([VISIBILITY_CXXFLAGS])
 
-dnl For some reason, the test for -Wno-foo always succeeds with gcc, even if the
-dnl option is not supported. Hence, check for -Wfoo instead.
-AX_CHECK_COMPILE_FLAG([-Woverride-init],                    [WNO_OVERRIDE_INIT="$WNO_OVERRIDE_INIT -Wno-override-init"])         # gcc
-AX_CHECK_COMPILE_FLAG([-Winitializer-overrides],            [WNO_OVERRIDE_INIT="$WNO_OVERRIDE_INIT -Wno-initializer-overrides"]) # clang
+AX_CHECK_COMPILE_FLAG([-Wno-override-init],                    [WNO_OVERRIDE_INIT="-Wno-override-init"])         # gcc
+AX_CHECK_COMPILE_FLAG([-Wno-initializer-overrides],            [WNO_OVERRIDE_INIT="-Wno-initializer-overrides"]) # clang
 AC_SUBST([WNO_OVERRIDE_INIT])
 
 dnl
@@ -685,19 +627,6 @@ AC_LINK_IFELSE(
 LDFLAGS=$save_LDFLAGS
 AM_CONDITIONAL(HAVE_LD_DYNAMIC_LIST, test "$have_ld_dynamic_list" = "yes")
 
-dnl
-dnl OSX linker does not support build-id
-dnl
-case "$host_os" in
-darwin*)
-    LD_BUILD_ID=""
-    ;;
-*)
-    LD_BUILD_ID="-Wl,--build-id=sha1"
-    ;;
-esac
-AC_SUBST([LD_BUILD_ID])
-
 dnl
 dnl compatibility symlinks
 dnl
@@ -862,10 +791,8 @@ fi
 AC_HEADER_MAJOR
 AC_CHECK_HEADER([xlocale.h], [DEFINES="$DEFINES -DHAVE_XLOCALE_H"])
 AC_CHECK_HEADER([sys/sysctl.h], [DEFINES="$DEFINES -DHAVE_SYS_SYSCTL_H"])
-AC_CHECK_HEADERS([endian.h])
 AC_CHECK_FUNC([strtof], [DEFINES="$DEFINES -DHAVE_STRTOF"])
 AC_CHECK_FUNC([mkostemp], [DEFINES="$DEFINES -DHAVE_MKOSTEMP"])
-AC_CHECK_FUNC([timespec_get], [DEFINES="$DEFINES -DHAVE_TIMESPEC_GET"])
 AC_CHECK_FUNC([memfd_create], [DEFINES="$DEFINES -DHAVE_MEMFD_CREATE"])
 
 AC_MSG_CHECKING([whether strtod has locale support])
@@ -920,7 +847,6 @@ AC_CHECK_FUNC([posix_memalign], [DEFINES="$DEFINES -DHAVE_POSIX_MEMALIGN"])
 
 dnl Check for zlib
 PKG_CHECK_MODULES([ZLIB], [zlib >= $ZLIB_REQUIRED])
-DEFINES="$DEFINES -DHAVE_ZLIB"
 
 dnl Check for pthreads
 AX_PTHREAD
@@ -940,10 +866,10 @@ dnl In practise that should be sufficient for all platforms, since any
 dnl platforms build with GCC and Clang support the flag.
 PTHREAD_LIBS="$PTHREAD_LIBS -pthread"
 
-dnl pthread-stubs is mandatory on some BSD platforms, due to the nature of the
+dnl pthread-stubs is mandatory on BSD platforms, due to the nature of the
 dnl project. Even then there's a notable issue as described in the project README
 case "$host_os" in
-linux* | cygwin* | darwin* | solaris* | *-gnu* | gnu* | openbsd*)
+linux* | cygwin* | darwin* | solaris* | *-gnu* | gnu*)
     pthread_stubs_possible="no"
     ;;
 * )
@@ -955,9 +881,6 @@ if test "x$pthread_stubs_possible" = xyes; then
     PKG_CHECK_MODULES(PTHREADSTUBS, pthread-stubs >= 0.4)
 fi
 
-dnl Check for futex for fast inline simple_mtx_t.
-AC_CHECK_HEADER([linux/futex.h], [DEFINES="$DEFINES -DHAVE_LINUX_FUTEX_H"])
-
 dnl SELinux awareness.
 AC_ARG_ENABLE([selinux],
     [AS_HELP_STRING([--enable-selinux],
@@ -1284,10 +1207,10 @@ AC_ARG_ENABLE([xa],
     [enable_xa=no])
 AC_ARG_ENABLE([gbm],
    [AS_HELP_STRING([--enable-gbm],
-         [enable gbm library @<:@default=yes except cygwin and macOS@:>@])],
+         [enable gbm library @<:@default=yes except cygwin@:>@])],
    [enable_gbm="$enableval"],
    [case "$host_os" in
-       cygwin* | darwin*)
+       cygwin*)
           enable_gbm=no
           ;;
        *)
@@ -1333,9 +1256,9 @@ AC_ARG_ENABLE([opencl],
 AC_ARG_ENABLE([opencl_icd],
    [AS_HELP_STRING([--enable-opencl-icd],
           [Build an OpenCL ICD library to be loaded by an ICD implementation
-           @<:@default=enabled@:>@])],
+           @<:@default=disabled@:>@])],
     [enable_opencl_icd="$enableval"],
-    [enable_opencl_icd=yes])
+    [enable_opencl_icd=no])
 
 AC_ARG_ENABLE([gallium-tests],
     [AS_HELP_STRING([--enable-gallium-tests],
@@ -1612,7 +1535,7 @@ fi
 AC_ARG_ENABLE([driglx-direct],
     [AS_HELP_STRING([--disable-driglx-direct],
         [disable direct rendering in GLX and EGL for DRI \
-            @<:@default=enabled@:>@])],
+            @<:@default=auto@:>@])],
     [driglx_direct="$enableval"],
     [driglx_direct="yes"])
 
@@ -2317,8 +2240,8 @@ if test "x$enable_opencl" = xyes; then
         AC_MSG_ERROR([cannot enable OpenCL without Gallium])
     fi
 
-    if test "x$HAVE_CXX11" != "xyes"; then
-       AC_MSG_ERROR([clover requires c++11 support])
+    if test $GCC_VERSION_MAJOR -lt 4 -o $GCC_VERSION_MAJOR -eq 4 -a $GCC_VERSION_MINOR -lt 7; then
+        AC_MSG_ERROR([gcc >= 4.7 is required to build clover])
     fi
 
     if test "x$have_libclc" = xno; then
@@ -2486,13 +2409,12 @@ dnl Surfaceless is an alternative for the last one.
 dnl
 require_basic_egl() {
     case "$with_platforms" in
-        *drm*|*surfaceless*|*android*)
+        *drm*|*surfaceless*)
             ;;
         *)
             AC_MSG_ERROR([$1 requires one of these:
                   1) --with-platforms=drm (X, Wayland, offscreen rendering based on DRM)
                   2) --with-platforms=surfaceless (offscreen only)
-                  3) --with-platforms=android (Android only)
                   Recommended options: drm,x11])
             ;;
     esac
@@ -2572,14 +2494,6 @@ if test -n "$with_gallium_drivers"; then
             HAVE_GALLIUM_RADEONSI=yes
             PKG_CHECK_MODULES([RADEON], [libdrm >= $LIBDRM_RADEON_REQUIRED libdrm_radeon >= $LIBDRM_RADEON_REQUIRED])
             PKG_CHECK_MODULES([AMDGPU], [libdrm >= $LIBDRM_AMDGPU_REQUIRED libdrm_amdgpu >= $LIBDRM_AMDGPU_REQUIRED])
-
-            # Blacklist libdrm_amdgpu 2.4.90 because it causes a crash in older
-            # radeonsi with pretty much any app.
-            libdrm_version=`pkg-config libdrm_amdgpu --modversion`
-            if test "x$libdrm_version" = x2.4.90; then
-                AC_MSG_ERROR([radeonsi can't use libdrm 2.4.90 due to a compatibility issue. Use a newer or older version.])
-            fi
-
             require_libdrm "radeonsi"
             radeon_llvm_check $LLVM_REQUIRED_RADEONSI "radeonsi"
             if test "x$enable_egl" = xyes; then
@@ -2613,9 +2527,10 @@ if test -n "$with_gallium_drivers"; then
         xswr)
             llvm_require_version $LLVM_REQUIRED_SWR "swr"
 
-            if test "x$HAVE_CXX11" != "xyes"; then
-                AC_MSG_ERROR([swr requires c++11 support])
-            fi
+            swr_require_cxx_feature_flags "C++11" "__cplusplus >= 201103L" \
+                ",-std=c++11" \
+                SWR_CXX11_CXXFLAGS
+            AC_SUBST([SWR_CXX11_CXXFLAGS])
 
             swr_require_cxx_feature_flags "AVX" "defined(__AVX__)" \
                 ",-target-cpu=sandybridge,-mavx,-march=core-avx,-tp=sandybridge" \
@@ -2662,11 +2577,6 @@ if test -n "$with_gallium_drivers"; then
                AC_MSG_ERROR([swr enabled but no swr architectures selected])
             fi
 
-            # test if more than one swr arch configured
-            if test `echo $swr_archs | wc -w` -eq 1; then
-                HAVE_SWR_BUILTIN=yes
-            fi
-
             HAVE_GALLIUM_SWR=yes
             ;;
         xvc4)
@@ -2716,7 +2626,6 @@ AM_CONDITIONAL(HAVE_SWR_AVX, test "x$HAVE_SWR_AVX" = xyes)
 AM_CONDITIONAL(HAVE_SWR_AVX2, test "x$HAVE_SWR_AVX2" = xyes)
 AM_CONDITIONAL(HAVE_SWR_KNL, test "x$HAVE_SWR_KNL" = xyes)
 AM_CONDITIONAL(HAVE_SWR_SKX, test "x$HAVE_SWR_SKX" = xyes)
-AM_CONDITIONAL(HAVE_SWR_BUILTIN, test "x$HAVE_SWR_BUILTIN" = xyes)
 
 dnl We need to validate some needed dependencies for renderonly drivers.
 
@@ -2802,18 +2711,6 @@ if test "x$enable_llvm" = xyes; then
             fi
         fi
     fi
-
-    dnl The gallium-xlib GLX and gallium OSMesa targets directly embed the
-    dnl swr/llvmpipe driver into the final binary.  Adding LLVM_LIBS results in 
-    dnl the LLVM library propagated in the Libs.private of the respective .pc
-    dnl file which ensures complete dependency information when statically
-    dnl linking.
-    if test "x$enable_glx" == xgallium-xlib; then
-        GL_PC_LIB_PRIV="$GL_PC_LIB_PRIV $LLVM_LIBS"
-    fi
-    if test "x$enable_gallium_osmesa" = xyes; then
-        OSMESA_PC_LIB_PRIV="$OSMESA_PC_LIB_PRIV $LLVM_LIBS"
-    fi
 fi
 
 AM_CONDITIONAL(HAVE_GALLIUM_SVGA, test "x$HAVE_GALLIUM_SVGA" = xyes)
@@ -2891,8 +2788,8 @@ AM_CONDITIONAL(HAVE_ARM_ASM, test "x$asm_arch" = xarm)
 
 AC_SUBST([NINE_MAJOR], 1)
 AC_SUBST([NINE_MINOR], 0)
-AC_SUBST([NINE_PATCH], 0)
-AC_SUBST([NINE_VERSION], "$NINE_MAJOR.$NINE_MINOR.$NINE_PATCH")
+AC_SUBST([NINE_TINY], 0)
+AC_SUBST([NINE_VERSION], "$NINE_MAJOR.$NINE_MINOR.$NINE_TINY")
 
 AC_SUBST([VDPAU_MAJOR], 1)
 AC_SUBST([VDPAU_MINOR], 0)
@@ -2909,10 +2806,15 @@ AM_CONDITIONAL(HAVE_VULKAN_COMMON, test "x$VULKAN_DRIVERS" != "x")
 AC_SUBST([XVMC_MAJOR], 1)
 AC_SUBST([XVMC_MINOR], 0)
 
-AC_SUBST([XA_MAJOR], 2)
-AC_SUBST([XA_MINOR], 3)
-AC_SUBST([XA_PATCH], 0)
-AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_PATCH")
+XA_HEADER="$srcdir/src/gallium/state_trackers/xa/xa_tracker.h"
+XA_MAJOR=`grep "#define XA_TRACKER_VERSION_MAJOR" $XA_HEADER | $SED 's/^#define XA_TRACKER_VERSION_MAJOR //'`
+XA_MINOR=`grep "#define XA_TRACKER_VERSION_MINOR" $XA_HEADER | $SED 's/^#define XA_TRACKER_VERSION_MINOR //'`
+XA_TINY=`grep "#define XA_TRACKER_VERSION_PATCH" $XA_HEADER | $SED 's/^#define XA_TRACKER_VERSION_PATCH //'`
+
+AC_SUBST([XA_MAJOR], $XA_MAJOR)
+AC_SUBST([XA_MINOR], $XA_MINOR)
+AC_SUBST([XA_TINY], $XA_TINY)
+AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_TINY")
 
 AC_ARG_ENABLE(valgrind,
               [AS_HELP_STRING([--enable-valgrind],
@@ -2994,7 +2896,6 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/state_trackers/va/Makefile
                  src/gallium/state_trackers/vdpau/Makefile
                  src/gallium/state_trackers/xa/Makefile
-                 src/gallium/state_trackers/xa/xa_tracker.h
                  src/gallium/state_trackers/xvmc/Makefile
                  src/gallium/targets/d3dadapter9/Makefile
                  src/gallium/targets/d3dadapter9/d3d.pc
@@ -3193,11 +3094,7 @@ fi
 
 echo ""
 if test "x$HAVE_GALLIUM_SWR" != x; then
-    if test "x$HAVE_SWR_BUILTIN" = xyes; then
-        echo "        SWR archs:       $swr_archs (builtin)"
-    else
-        echo "        SWR archs:       $swr_archs"
-    fi
+    echo "        SWR archs:       $swr_archs"
 fi
 
 dnl Libraries
@@ -3217,7 +3114,6 @@ defines=`echo $DEFINES | $SED 's/^ *//;s/  */ /;s/ *$//'`
 echo ""
 echo "        CFLAGS:          $cflags"
 echo "        CXXFLAGS:        $cxxflags"
-echo "        CXX11_CXXFLAGS:  $CXX11_CXXFLAGS"
 echo "        LDFLAGS:         $ldflags"
 echo "        Macros:          $defines"
 echo ""

docs/contents.html

@@ -43,7 +43,6 @@
 <li><a href="install.html" target="_parent">Compiling / Installing</a>
   <ul>
     <li><a href="autoconf.html" target="_parent">Autoconf</a></li>
-    <li><a href="meson.html" target="_parent">Meson</a></li>
   </ul>
 </li>
 <li><a href="precompiled.html" target="_parent">Precompiled Libraries</a>

docs/envvars.html

@@ -88,40 +88,22 @@ This is a work-around for that.
 <li>MESA_GL_VERSION_OVERRIDE - changes the value returned by
 glGetString(GL_VERSION) and possibly the GL API type.
 <ul>
-  <li>The format should be MAJOR.MINOR[FC|COMPAT]
-  <li>FC is an optional suffix that indicates a forward compatible
-      context. This is only valid for versions &gt;= 3.0.
-  <li>COMPAT is an optional suffix that indicates a compatibility
-      context or GL_ARB_compatibility support. This is only valid for
-      versions &gt;= 3.1.
-  <li>GL versions &lt;= 3.0 are set to a compatibility (non-Core)
-      profile
-  <li>GL versions = 3.1, depending on the driver, it may or may not
-      have the ARB_compatibility extension enabled.
-  <li>GL versions &gt;= 3.2 are set to a Core profile
-  <li>Examples: 2.1, 3.0, 3.0FC, 3.1, 3.1FC, 3.1COMPAT, X.Y, X.YFC,
-      X.YCOMPAT.
-  <ul>
-    <li>2.1 - select a compatibility (non-Core) profile with GL
-        version 2.1.
-    <li>3.0 - select a compatibility (non-Core) profile with GL
-        version 3.0.
-    <li>3.0FC - select a Core+Forward Compatible profile with GL
-        version 3.0.
-    <li>3.1 - select GL version 3.1 with GL_ARB_compatibility enabled
-        per the driver default.
-    <li>3.1FC - select GL version 3.1 with forward compatibility and
-        GL_ARB_compatibility disabled.
-    <li>3.1COMPAT - select GL version 3.1 with GL_ARB_compatibility
-        enabled.
-    <li>X.Y - override GL version to X.Y without changing the profile.
-    <li>X.YFC - select a Core+Forward Compatible profile with GL
-        version X.Y.
-    <li>X.YCOMPAT - select a Compatibility profile with GL version
-        X.Y.
-  </ul>
-  <li>Mesa may not really implement all the features of the given
-      version. (for developers only)
+<li> The format should be MAJOR.MINOR[FC]
+<li> FC is an optional suffix that indicates a forward compatible context.
+This is only valid for versions &gt;= 3.0.
+<li> GL versions &lt; 3.0 are set to a compatibility (non-Core) profile
+<li> GL versions = 3.0, see below
+<li> GL versions &gt; 3.0 are set to a Core profile
+<li> Examples: 2.1, 3.0, 3.0FC, 3.1, 3.1FC
+<ul>
+<li> 2.1 - select a compatibility (non-Core) profile with GL version 2.1
+<li> 3.0 - select a compatibility (non-Core) profile with GL version 3.0
+<li> 3.0FC - select a Core+Forward Compatible profile with GL version 3.0
+<li> 3.1 - select a Core profile with GL version 3.1
+<li> 3.1FC - select a Core+Forward Compatible profile with GL version 3.1
+</ul>
+<li> Mesa may not really implement all the features of the given version.
+(for developers only)
 </ul>
 <li>MESA_GLES_VERSION_OVERRIDE - changes the value returned by
 glGetString(GL_VERSION) for OpenGL ES.

docs/extensions.html

@@ -23,7 +23,7 @@ The specifications follow.
 
 
 <ul>
-<li><a href="specs/OLD/MESA_agp_offset.spec">MESA_agp_offset.spec</a>
+<li><a href="specs/MESA_agp_offset.spec">MESA_agp_offset.spec</a>
 <li><a href="specs/MESA_copy_sub_buffer.spec">MESA_copy_sub_buffer.spec</a>
 <li><a href="specs/MESA_drm_image.spec">MESA_drm_image.spec</a>
 <li><a href="specs/MESA_multithread_makecurrent.spec">MESA_multithread_makecurrent.spec</a>
@@ -33,7 +33,7 @@ The specifications follow.
 <li><a href="specs/OLD/MESA_program_debug.spec">MESA_program_debug.spec</a> (obsolete)
 <li><a href="specs/MESA_release_buffers.spec">MESA_release_buffers.spec</a>
 <li><a href="specs/OLD/MESA_resize_buffers.spec">MESA_resize_buffers.spec</a> (obsolete)
-<li><a href="specs/OLD/MESA_set_3dfx_mode.spec">MESA_set_3dfx_mode.spec</a>
+<li><a href="specs/MESA_set_3dfx_mode.spec">MESA_set_3dfx_mode.spec</a>
 <li><a href="specs/MESA_shader_debug.spec">MESA_shader_debug.spec</a>
 <li><a href="specs/OLD/MESA_sprite_point.spec">MESA_sprite_point.spec</a> (obsolete)
 <li><a href="specs/MESA_swap_control.spec">MESA_swap_control.spec</a>

docs/features.txt

@@ -102,7 +102,7 @@ GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, soft
   GL_ARB_shader_bit_encoding                            DONE (freedreno, swr)
   GL_ARB_texture_rgb10_a2ui                             DONE (freedreno, swr)
   GL_ARB_texture_swizzle                                DONE (freedreno, swr)
-  GL_ARB_timer_query                                    DONE (freedreno, swr)
+  GL_ARB_timer_query                                    DONE (swr)
   GL_ARB_instanced_arrays                               DONE (freedreno, swr)
   GL_ARB_vertex_type_2_10_10_10_rev                     DONE (freedreno, swr)
 
@@ -110,7 +110,7 @@ GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, soft
 GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
 
   GL_ARB_draw_buffers_blend                             DONE (freedreno, i965/gen6+, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_draw_indirect                                  DONE (freedreno, i965/gen7+, llvmpipe, softpipe, swr)
+  GL_ARB_draw_indirect                                  DONE (i965/gen7+, llvmpipe, softpipe, swr)
   GL_ARB_gpu_shader5                                    DONE (i965/gen7+)
   - 'precise' qualifier                                 DONE
   - Dynamically uniform sampler array indices           DONE (softpipe)
@@ -126,97 +126,97 @@ GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
   - New overload resolution rules                       DONE
   GL_ARB_gpu_shader_fp64                                DONE (i965/gen7+, llvmpipe, softpipe)
   GL_ARB_sample_shading                                 DONE (i965/gen6+, nv50)
-  GL_ARB_shader_subroutine                              DONE (freedreno, i965/gen6+, nv50, llvmpipe, softpipe, swr)
+  GL_ARB_shader_subroutine                              DONE (i965/gen6+, nv50, llvmpipe, softpipe, swr)
   GL_ARB_tessellation_shader                            DONE (i965/gen7+)
-  GL_ARB_texture_buffer_object_rgb32                    DONE (freedreno, i965/gen6+, llvmpipe, softpipe, swr)
+  GL_ARB_texture_buffer_object_rgb32                    DONE (i965/gen6+, llvmpipe, softpipe, swr)
   GL_ARB_texture_cube_map_array                         DONE (i965/gen6+, nv50, llvmpipe, softpipe)
-  GL_ARB_texture_gather                                 DONE (freedreno, i965/gen6+, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_texture_query_lod                              DONE (freedreno, i965, nv50, llvmpipe, softpipe)
+  GL_ARB_texture_gather                                 DONE (i965/gen6+, nv50, llvmpipe, softpipe, swr)
+  GL_ARB_texture_query_lod                              DONE (i965, nv50, llvmpipe, softpipe)
   GL_ARB_transform_feedback2                            DONE (i965/gen6+, nv50, llvmpipe, softpipe, swr)
   GL_ARB_transform_feedback3                            DONE (i965/gen7+, llvmpipe, softpipe, swr)
 
 
 GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
 
-  GL_ARB_ES2_compatibility                              DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_get_program_binary                             DONE (0 or 1 binary formats)
+  GL_ARB_ES2_compatibility                              DONE (i965, nv50, llvmpipe, softpipe, swr)
+  GL_ARB_get_program_binary                             DONE (0 binary formats)
   GL_ARB_separate_shader_objects                        DONE (all drivers)
   GL_ARB_shader_precision                               DONE (i965/gen7+, all drivers that support GLSL 4.10)
   GL_ARB_vertex_attrib_64bit                            DONE (i965/gen7+, llvmpipe, softpipe)
   GL_ARB_viewport_array                                 DONE (i965, nv50, llvmpipe, softpipe)
 
 
-GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi
+GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, radeonsi
 
-  GL_ARB_texture_compression_bptc                       DONE (freedreno, i965)
+  GL_ARB_texture_compression_bptc                       DONE (i965, r600)
   GL_ARB_compressed_texture_pixel_storage               DONE (all drivers)
-  GL_ARB_shader_atomic_counters                         DONE (freedreno/a5xx, i965, softpipe)
+  GL_ARB_shader_atomic_counters                         DONE (i965, softpipe)
   GL_ARB_texture_storage                                DONE (all drivers)
-  GL_ARB_transform_feedback_instanced                   DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_base_instance                                  DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_shader_image_load_store                        DONE (freedreno/a5xx, i965, softpipe)
+  GL_ARB_transform_feedback_instanced                   DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_base_instance                                  DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_shader_image_load_store                        DONE (i965, softpipe)
   GL_ARB_conservative_depth                             DONE (all drivers that support GLSL 1.30)
   GL_ARB_shading_language_420pack                       DONE (all drivers that support GLSL 1.30)
   GL_ARB_shading_language_packing                       DONE (all drivers)
-  GL_ARB_internalformat_query                           DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr)
+  GL_ARB_internalformat_query                           DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
   GL_ARB_map_buffer_alignment                           DONE (all drivers)
 
 
-GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
+GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, radeonsi
 
   GL_ARB_arrays_of_arrays                               DONE (all drivers that support GLSL 1.30)
   GL_ARB_ES3_compatibility                              DONE (all drivers that support GLSL 3.30)
   GL_ARB_clear_buffer_object                            DONE (all drivers)
-  GL_ARB_compute_shader                                 DONE (freedreno/a5xx, i965, softpipe)
-  GL_ARB_copy_image                                     DONE (i965, nv50, softpipe, llvmpipe)
+  GL_ARB_compute_shader                                 DONE (i965, softpipe)
+  GL_ARB_copy_image                                     DONE (i965, nv50, r600, softpipe, llvmpipe)
   GL_KHR_debug                                          DONE (all drivers)
   GL_ARB_explicit_uniform_location                      DONE (all drivers that support GLSL)
-  GL_ARB_fragment_layer_viewport                        DONE (i965, nv50, llvmpipe, softpipe)
-  GL_ARB_framebuffer_no_attachments                     DONE (freedreno, i965, softpipe)
+  GL_ARB_fragment_layer_viewport                        DONE (i965, nv50, r600, llvmpipe, softpipe)
+  GL_ARB_framebuffer_no_attachments                     DONE (i965, r600, softpipe)
   GL_ARB_internalformat_query2                          DONE (all drivers)
   GL_ARB_invalidate_subdata                             DONE (all drivers)
-  GL_ARB_multi_draw_indirect                            DONE (freedreno, i965, llvmpipe, softpipe, swr)
+  GL_ARB_multi_draw_indirect                            DONE (i965, r600, llvmpipe, softpipe, swr)
   GL_ARB_program_interface_query                        DONE (all drivers)
   GL_ARB_robust_buffer_access_behavior                  DONE (i965)
-  GL_ARB_shader_image_size                              DONE (freedreno/a5xx, i965, softpipe)
-  GL_ARB_shader_storage_buffer_object                   DONE (freedreno/a5xx, i965, softpipe)
-  GL_ARB_stencil_texturing                              DONE (freedreno, i965/hsw+, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_texture_buffer_range                           DONE (freedreno, nv50, i965, llvmpipe)
+  GL_ARB_shader_image_size                              DONE (i965, softpipe)
+  GL_ARB_shader_storage_buffer_object                   DONE (i965, softpipe)
+  GL_ARB_stencil_texturing                              DONE (i965/hsw+, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_texture_buffer_range                           DONE (nv50, i965, r600, llvmpipe)
   GL_ARB_texture_query_levels                           DONE (all drivers that support GLSL 1.30)
   GL_ARB_texture_storage_multisample                    DONE (all drivers that support GL_ARB_texture_multisample)
-  GL_ARB_texture_view                                   DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr)
+  GL_ARB_texture_view                                   DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
   GL_ARB_vertex_attrib_binding                          DONE (all drivers)
 
 
 GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, radeonsi
 
   GL_MAX_VERTEX_ATTRIB_STRIDE                           DONE (all drivers)
-  GL_ARB_buffer_storage                                 DONE (freedreno, i965, nv50, r600, llvmpipe, swr)
+  GL_ARB_buffer_storage                                 DONE (i965, nv50, r600, llvmpipe, swr)
   GL_ARB_clear_texture                                  DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
-  GL_ARB_enhanced_layouts                               DONE (i965, nv50, r600, llvmpipe, softpipe)
+  GL_ARB_enhanced_layouts                               DONE (i965, nv50, llvmpipe, softpipe)
   - compile-time constant expressions                   DONE
   - explicit byte offsets for blocks                    DONE
   - forced alignment within blocks                      DONE
-  - specified vec4-slot component numbers               DONE
+  - specified vec4-slot component numbers               DONE (i965, nv50, llvmpipe, softpipe)
   - specified transform/feedback layout                 DONE
   - input/output block locations                        DONE
   GL_ARB_multi_bind                                     DONE (all drivers)
   GL_ARB_query_buffer_object                            DONE (i965/hsw+)
   GL_ARB_texture_mirror_clamp_to_edge                   DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
-  GL_ARB_texture_stencil8                               DONE (freedreno, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_texture_stencil8                               DONE (i965/hsw+, nv50, r600, llvmpipe, softpipe, swr)
   GL_ARB_vertex_type_10f_11f_11f_rev                    DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
 
 GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
 
-  GL_ARB_ES3_1_compatibility                            DONE (i965/hsw+, r600)
-  GL_ARB_clip_control                                   DONE (freedreno, i965, nv50, r600, llvmpipe, softpipe, swr)
-  GL_ARB_conditional_render_inverted                    DONE (freedreno, i965, nv50, r600, llvmpipe, softpipe, swr)
-  GL_ARB_cull_distance                                  DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_ES3_1_compatibility                            DONE (i965/hsw+)
+  GL_ARB_clip_control                                   DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_conditional_render_inverted                    DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_cull_distance                                  DONE (i965, nv50, llvmpipe, softpipe, swr)
   GL_ARB_derivative_control                             DONE (i965, nv50, r600)
   GL_ARB_direct_state_access                            DONE (all drivers)
   GL_ARB_get_texture_sub_image                          DONE (all drivers)
   GL_ARB_shader_texture_image_samples                   DONE (i965, nv50, r600)
-  GL_ARB_texture_barrier                                DONE (freedreno, i965, nv50, r600)
+  GL_ARB_texture_barrier                                DONE (i965, nv50, r600)
   GL_KHR_context_flush_control                          DONE (all - but needs GLX/EGL extension to be useful)
   GL_KHR_robustness                                     DONE (i965)
   GL_EXT_shader_integer_mix                             DONE (all drivers that support GLSL)
@@ -225,39 +225,39 @@ GL 4.6, GLSL 4.60
 
   GL_ARB_gl_spirv                                       in progress (Nicolai Hähnle, Ian Romanick)
   GL_ARB_indirect_parameters                            DONE (i965/gen7+, nvc0, radeonsi)
-  GL_ARB_pipeline_statistics_query                      DONE (i965, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
-  GL_ARB_polygon_offset_clamp                           DONE (freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, swr)
-  GL_ARB_shader_atomic_counter_ops                      DONE (freedreno/a5xx, i965/gen7+, nvc0, r600, radeonsi, softpipe)
+  GL_ARB_pipeline_statistics_query                      DONE (i965, nvc0, radeonsi, llvmpipe, softpipe, swr)
+  GL_ARB_polygon_offset_clamp                           DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, swr)
+  GL_ARB_shader_atomic_counter_ops                      DONE (i965/gen7+, nvc0, radeonsi, softpipe)
   GL_ARB_shader_draw_parameters                         DONE (i965, nvc0, radeonsi)
   GL_ARB_shader_group_vote                              DONE (i965, nvc0, radeonsi)
   GL_ARB_spirv_extensions                               in progress (Nicolai Hähnle, Ian Romanick)
-  GL_ARB_texture_filter_anisotropic                     DONE (freedreno, i965, nv50, nvc0, r600, radeonsi, softpipe (*), llvmpipe (*))
+  GL_ARB_texture_filter_anisotropic                     DONE (i965, nv50, nvc0, r600, radeonsi, softpipe (*), llvmpipe (*))
   GL_ARB_transform_feedback_overflow_query              DONE (i965/gen6+, radeonsi, llvmpipe, softpipe)
-  GL_KHR_no_error                                       DONE (all drivers)
+  GL_KHR_no_error                                       started (Timothy Arceri)
 
 (*) softpipe and llvmpipe advertise 16x anisotropy but simply ignore the setting
 
 These are the extensions cherry-picked to make GLES 3.1
-GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, r600, radeonsi
+GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, radeonsi
 
   GL_ARB_arrays_of_arrays                               DONE (all drivers that support GLSL 1.30)
-  GL_ARB_compute_shader                                 DONE (freedreno/a5xx, i965/gen7+, softpipe)
-  GL_ARB_draw_indirect                                  DONE (freedreno, i965/gen7+, llvmpipe, softpipe, swr)
+  GL_ARB_compute_shader                                 DONE (i965/gen7+, softpipe)
+  GL_ARB_draw_indirect                                  DONE (i965/gen7+, r600, llvmpipe, softpipe, swr)
   GL_ARB_explicit_uniform_location                      DONE (all drivers that support GLSL)
-  GL_ARB_framebuffer_no_attachments                     DONE (freedreno, i965/gen7+, softpipe)
+  GL_ARB_framebuffer_no_attachments                     DONE (i965/gen7+, r600, softpipe)
   GL_ARB_program_interface_query                        DONE (all drivers)
-  GL_ARB_shader_atomic_counters                         DONE (freedreno/a5xx, i965/gen7+, softpipe)
-  GL_ARB_shader_image_load_store                        DONE (freedreno/a5xx, i965/gen7+, softpipe)
-  GL_ARB_shader_image_size                              DONE (freedreno/a5xx, i965/gen7+, softpipe)
-  GL_ARB_shader_storage_buffer_object                   DONE (freedreno/a5xx, i965/gen7+, softpipe)
+  GL_ARB_shader_atomic_counters                         DONE (i965/gen7+, softpipe)
+  GL_ARB_shader_image_load_store                        DONE (i965/gen7+, softpipe)
+  GL_ARB_shader_image_size                              DONE (i965/gen7+, softpipe)
+  GL_ARB_shader_storage_buffer_object                   DONE (i965/gen7+, softpipe)
   GL_ARB_shading_language_packing                       DONE (all drivers)
   GL_ARB_separate_shader_objects                        DONE (all drivers)
-  GL_ARB_stencil_texturing                              DONE (freedreno, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_texture_multisample (Multisample textures)     DONE (i965/gen7+, nv50, llvmpipe, softpipe)
+  GL_ARB_stencil_texturing                              DONE (nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_texture_multisample (Multisample textures)     DONE (i965/gen7+, nv50, r600, llvmpipe, softpipe)
   GL_ARB_texture_storage_multisample                    DONE (all drivers that support GL_ARB_texture_multisample)
   GL_ARB_vertex_attrib_binding                          DONE (all drivers)
-  GS5 Enhanced textureGather                            DONE (freedreno, i965/gen7+,)
-  GS5 Packing/bitfield/conversion functions             DONE (i965/gen6+)
+  GS5 Enhanced textureGather                            DONE (i965/gen7+, r600)
+  GS5 Packing/bitfield/conversion functions             DONE (i965/gen6+, r600)
   GL_EXT_shader_integer_mix                             DONE (all drivers that support GLSL)
 
   Additional functionality not covered above:
@@ -272,7 +272,7 @@ GLES3.2, GLSL ES 3.2 -- all DONE: i965/gen9+
   GL_KHR_blend_equation_advanced                        DONE (i965, nvc0)
   GL_KHR_debug                                          DONE (all drivers)
   GL_KHR_robustness                                     DONE (i965, nvc0, radeonsi)
-  GL_KHR_texture_compression_astc_ldr                   DONE (freedreno, i965/gen9+)
+  GL_KHR_texture_compression_astc_ldr                   DONE (i965/gen9+)
   GL_OES_copy_image                                     DONE (all drivers)
   GL_OES_draw_buffers_indexed                           DONE (all drivers that support GL_ARB_draw_buffers_blend)
   GL_OES_draw_elements_base_vertex                      DONE (all drivers)
@@ -293,7 +293,7 @@ GLES3.2, GLSL ES 3.2 -- all DONE: i965/gen9+
 
 Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES version:
 
-  GL_ARB_bindless_texture                               DONE (nvc0, radeonsi)
+  GL_ARB_bindless_texture                               DONE (radeonsi)
   GL_ARB_cl_event                                       not started
   GL_ARB_compute_variable_group_size                    DONE (nvc0, radeonsi)
   GL_ARB_ES3_2_compatibility                            DONE (i965/gen8+)
@@ -305,8 +305,8 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_ARB_sample_locations                               not started
   GL_ARB_seamless_cubemap_per_texture                   DONE (i965, nvc0, radeonsi, r600, softpipe, swr)
   GL_ARB_shader_ballot                                  DONE (i965/gen8+, nvc0, radeonsi)
-  GL_ARB_shader_clock                                   DONE (i965/gen7+, nv50, nvc0, r600, radeonsi)
-  GL_ARB_shader_stencil_export                          DONE (i965/gen9+, r600, radeonsi, softpipe, llvmpipe, swr)
+  GL_ARB_shader_clock                                   DONE (i965/gen7+, nv50, nvc0, radeonsi)
+  GL_ARB_shader_stencil_export                          DONE (i965/gen9+, radeonsi, softpipe, llvmpipe, swr)
   GL_ARB_shader_viewport_layer_array                    DONE (i965/gen6+, nvc0, radeonsi)
   GL_ARB_sparse_buffer                                  DONE (radeonsi/CIK+)
   GL_ARB_sparse_texture                                 not started
@@ -328,10 +328,10 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_OES_required_internalformat                        DONE (all drivers)
   GL_OES_surfaceless_context                            DONE (all drivers)
   GL_OES_texture_compression_astc                       DONE (core only)
-  GL_OES_texture_float                                  DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
-  GL_OES_texture_float_linear                           DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
-  GL_OES_texture_half_float                             DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
-  GL_OES_texture_half_float_linear                      DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
+  GL_OES_texture_float                                  DONE (i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
+  GL_OES_texture_float_linear                           DONE (i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
+  GL_OES_texture_half_float                             DONE (i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
+  GL_OES_texture_half_float_linear                      DONE (i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
   GL_OES_texture_view                                   not started - based on GL_ARB_texture_view
   GL_OES_viewport_array                                 DONE (i965, nvc0, radeonsi)
   GLX_ARB_context_flush_control                         not started

docs/index.html

@@ -16,65 +16,6 @@
 
 <h1>News</h1>
 
-<h2>January 18, 2018</h2>
-<p>
-<a href="relnotes/17.3.3.html">Mesa 17.3.3</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>January 8, 2018</h2>
-<p>
-<a href="relnotes/17.3.2.html">Mesa 17.3.2</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>December 22, 2017</h2>
-<p>
-<a href="relnotes/17.2.8.html">Mesa 17.2.8</a> is released.
-This is a bug-fix release.
-<br>
-NOTE: It is anticipated that 17.2.8 will be the final release in the
-17.2 series. Users of 17.2 are encouraged to migrate to the 17.3
-series in order to obtain future fixes.
-</p>
-
-<h2>December 21, 2017</h2>
-<p>
-<a href="relnotes/17.3.1.html">Mesa 17.3.1</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>December 14, 2017</h2>
-<p>
-<a href="relnotes/17.2.7.html">Mesa 17.2.7</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>December 8, 2017</h2>
-<p>
-<a href="relnotes/17.3.0.html">Mesa 17.3.0</a> is released.  This is a
-new development release.  See the release notes for more information
-about the release.
-</p>
-
-<h2>November 25, 2017</h2>
-<p>
-<a href="relnotes/17.2.6.html">Mesa 17.2.6</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>November 10, 2017</h2>
-<p>
-<a href="relnotes/17.2.5.html">Mesa 17.2.5</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>October 30, 2017</h2>
-<p>
-<a href="relnotes/17.2.4.html">Mesa 17.2.4</a> is released.
-This is a bug-fix release.
-</p>
-
 <h2>October 19, 2017</h2>
 <p>
 <a href="relnotes/17.2.3.html">Mesa 17.2.3</a> is released.
@@ -91,10 +32,6 @@ This is a bug-fix release.
 <p>
 <a href="relnotes/17.1.10.html">Mesa 17.1.10</a> is released.
 This is a bug-fix release.
-<br>
-NOTE: It is anticipated that 17.1.10 will be the final release in the
-17.1 series. Users of 17.1 are encouraged to migrate to the 17.2
-series in order to obtain future fixes.
 </p>
 
 <h2>September 17, 2017</h2>

docs/llvmpipe.html

@@ -20,7 +20,7 @@
 The Gallium llvmpipe driver is a software rasterizer that uses LLVM to
 do runtime code generation.
 Shaders, point/line/triangle rasterization and vertex processing are
-implemented with LLVM IR which is translated to x86, x86-64, or ppc64le machine
+implemented with LLVM IR which is translated to x86 or x86-64 machine
 code.
 Also, the driver is multithreaded to take advantage of multiple CPU cores
 (up to 8 at this time).
@@ -32,24 +32,18 @@ It's the fastest software rasterizer for Mesa.
 
 <ul>
 <li>
+   <p>For x86 or amd64 processors, 64-bit mode is recommended.</p>
    <p>
-   For x86 or amd64 processors, 64-bit mode is recommended.
    Support for SSE2 is strongly encouraged.  Support for SSE3 and SSE4.1 will
    yield the most efficient code.  The fewer features the CPU has the more
    likely it is that you will run into underperforming, buggy, or incomplete code.
    </p>
    <p>
-   For ppc64le processors, use of the Altivec feature (the Vector
-   Facility) is recommended if supported; use of the VSX feature (the
-   Vector-Scalar Facility) is recommended if supported AND Mesa is
-   built with LLVM version 4.0 or later.
-   </p>
-   <p>
    See /proc/cpuinfo to know what your CPU supports.
    </p>
 </li>
 <li>
-   <p>Unless otherwise stated, LLVM version 3.4 is recommended; 3.3 or later is required.</p>
+   <p>LLVM: version 3.4 recommended; 3.3 or later required.</p>
    <p>
    For Linux, on a recent Debian based distribution do:
    </p>
@@ -120,10 +114,10 @@ To build everything on Linux invoke scons as:
   scons build=debug libgl-xlib
 </pre>
 
-Alternatively, you can build it with autoconf/make with:
+Alternatively, you can build it with GNU make, if you prefer, by invoking it as
+
 <pre>
-  ./configure --enable-glx=gallium-xlib --with-gallium-drivers=swrast --disable-dri --disable-gbm --disable-egl
-  make
+  make linux-llvm
 </pre>
 
 but the rest of these instructions assume that scons is used.

docs/meson.html

@@ -1,168 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Compilation and Installation using Meson</title>
-  <link rel="stylesheet" type="text/css" href="mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="contents.html"></iframe>
-<div class="content">
-
-<h1>Compilation and Installation using Meson</h1>
-
-<h2 id="basic">1. Basic Usage</h2>
-
-<p><strong>The Meson build system for Mesa is still under active development,
-and should not be used in production environments.</strong></p>
-
-<p>The meson build is currently only tested on linux, and is known to not work
-on macOS, Windows, and haiku. This will be fixed.</p>
-
-<p>
-The meson program is used to configure the source directory and generates
-either a ninja build file or Visual Studio® build files. The latter must
-be enabled via the --backend switch, as ninja is the default backend on all
-operating systems. Meson only supports out-of-tree builds, and must be passed a
-directory to put built and generated sources into. We'll call that directory
-"build" for examples.
-</p>
-
-<pre>
-    meson build/
-</pre>
-
-<p>
-To see a description of your options you can run <code>meson configure</code>
-along with a build directory to view the selected options for. This will show
-your meson global arguments and project arguments, along with their defaults
-and your local settings.
-
-Moes does not currently support listing options before configure a build
-directory, but this feature is being discussed upstream.
-</p>
-
-<pre>
-    meson configure build/
-</pre>
-
-<p>
-With additional arguments <code>meson configure</code> is used to change
-options on already configured build directory. All options passed to this
-command are in the form -D "command"="value".
-</p>
-
-<pre>
-    meson configure build/ -Dprefix=/tmp/install -Dglx=true
-</pre>
-
-<p>
-Once you've run the initial <code>meson</code> command successfully you can use
-your configured backend to build the project. With ninja, the -C option can be
-be used to point at a directory to build.
-</p>
-
-<pre>
-    ninja -C build/
-</pre>
-
-<p>
-Without arguments, it will produce libGL.so and/or several other libraries
-depending on the options you have chosen. Later, if you want to rebuild for a
-different configuration, you should run <code>ninja clean</code> before
-changing the configuration, or create a new out of tree build directory for
-each configuration you want to build.
-
-http://mesonbuild.com/Using-multiple-build-directories.html
-</p>
-
-<dt><code>Environment Variables</code></dt>
-<dd><p>Meson supports the standard CC and CXX envrionment variables for
-changing the default compiler, and CFLAGS, CXXFLAGS, and LDFLAGS for setting
-options to the compiler and linker.
-
-The default compilers depends on your operating system. Meson supports most of
-the popular compilers, a complete list is available
-<a href="http://mesonbuild.com/Reference-tables.html#compiler-ids">here</a>.
-
-These arguments are consumed and stored by meson when it is initialized or
-re-initialized. Therefore passing them to meson configure will not do anything,
-and passing them to ninja will only do something if ninja decides to
-re-initialze meson, for example, if a meson.build file has been changed.
-Changing these variables will not cause all targets to be rebuilt, so running
-ninja clean is recomended when changing CFLAGS or CXXFLAGS. meson will never
-change compiler in a configured build directory.
-</p>
-
-<pre>
-    CC=clang CXX=clang++ meson build-clang
-    ninja -C build-clang
-    ninja -C build-clang clean
-    touch meson.build
-    CFLAGS=-Wno-typedef-redefinition ninja -C build-clang
-</pre>
-
-<p>Meson also honors DESTDIR for installs</p>
-</dd>
-
-
-<dt><code>LLVM</code></dt>
-<dd><p>Meson includes upstream logic to wrap llvm-config using it's standard
-dependncy interface. It will search $PATH (or %PATH% on windows) for
-llvm-config, so using an LLVM from a non-standard path is as easy as
-<code>PATH=/path/with/llvm-config:$PATH meson build</code>.
-</p></dd>
-</dl>
-
-<dt><code>PKG_CONFIG_PATH</code></dt>
-<dd><p>The
-<code>pkg-config</code> utility is a hard requirement for configuring and
-building Mesa on Linux and *BSD. It is used to search for external libraries
-on the system. This environment variable is used to control the search
-path for <code>pkg-config</code>. For instance, setting
-<code>PKG_CONFIG_PATH=/usr/X11R6/lib/pkgconfig</code> will search for
-package metadata in <code>/usr/X11R6</code> before the standard
-directories.</p>
-</dd>
-</dl>
-
-<p>
-One of the oddities of meson is that some options are different when passed to
-the <code>meson</code> than to <code>meson configure</code>. These options are
-passed as --option=foo to <code>meson</code>, but -Doption=foo to <code>meson
-configure</code>. Mesa defined options are always passed as -Doption=foo.
-<p>
-
-<p>For those coming from autotools be aware of the following:</p>
-
-<dl>
-<dt><code>--buildtype/-Dbuildtype</code></dt>
-<dd><p>This option will set the compiler debug/optimisation levels to aid
-debugging the Mesa libraries.</p>
-
-<p>Note that in meson this defaults to "debugoptimized", and  not setting it to
-"release" will yield non-optimal performance and binary size. Not using "debug"
-may interfer with debbugging as some code and validation will be optimized
-away.
-</p>
-
-<p> For those wishing to pass their own -O option, use the "plain" buildtype,
-which cuases meson to inject no additional compiler arguments, only those in
-the C/CXXFLAGS and those that mesa itself defines.</p>
-</dd>
-</dl>
-
-<dl>
-<dt><code>-Db_ndebug</code></dt>
-<dd><p>This option controls assertions in meson projects. When set to false
-(the default) assertions are enabled, when set to true they are disabled. This
-is unrelated to the <code>buildtype</code>; setting the latter to
-<code>release</code> will not turn off assertions.
-</p>
-</dd>
-</dl>

docs/release-calendar.html

@@ -39,67 +39,73 @@ if you'd like to nominate a patch in the next stable release.
 <th>Notes</th>
 </tr>
 <tr>
-<td rowspan="3">17.3</td>
-<td>2018-01-26</td>
-<td>17.3.4</td>
-<td>Emil Velikov</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-02-09</td>
-<td>17.3.5</td>
-<td>Juan A. Suarez Romero</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-02-23</td>
-<td>17.3.6</td>
-<td>Juan A. Suarez Romero</td>
-<td>Final planned release for the 17.3 series</td>
-</tr>
-<tr>
-<td rowspan="7">18.0</td>
-<td>2018-01-19</td>
-<td>18.0.0-rc1</td>
-<td>Emil Velikov</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-01-26</td>
-<td>18.0.0-rc2</td>
-<td>Emil Velikov</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-02-02</td>
-<td>18.0.0-rc3</td>
-<td>Emil Velikov</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-02-09</td>
-<td>18.0.0-rc4</td>
-<td>Emil Velikov</td>
-<td>May be promoted to 18.0.0 final</td>
-</tr>
-<tr>
-<td>2018-02-23</td>
-<td>18.0.1</td>
+<td rowspan="4">17.2</td>
+<td>2017-10-27</td>
+<td>17.2.4</td>
 <td>Andres Gomez</td>
 <td></td>
 </tr>
 <tr>
-<td>2018-03-09</td>
-<td>18.0.2</td>
+<td>2017-11-10</td>
+<td>17.2.5</td>
 <td>Andres Gomez</td>
 <td></td>
 </tr>
 <tr>
-<td>2018-03-23</td>
-<td>18.0.3</td>
+<td>2017-11-24</td>
+<td>17.2.6</td>
 <td>Andres Gomez</td>
 <td></td>
 </tr>
+<tr>
+<td>2017-12-08</td>
+<td>17.2.7</td>
+<td>Emil Velikov</td>
+<td>Final planned release for the 17.2 series</td>
+</tr>
+<tr>
+<td rowspan="7">17.3</td>
+<td>2017-10-20</td>
+<td>17.3.0-rc1</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>2017-10-27</td>
+<td>17.3.0-rc2</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>2017-11-03</td>
+<td>17.3.0-rc3</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>2017-11-10</td>
+<td>17.3.0-rc4</td>
+<td>Emil Velikov</td>
+<td>May be promoted to 17.3.0 final</td>
+</tr>
+<tr>
+<td>2017-11-24</td>
+<td>17.3.1</td>
+<td>Andres Gomez</td>
+<td></td>
+</tr>
+<tr>
+<td>2017-12-08</td>
+<td>17.3.2</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>2017-12-22</td>
+<td>17.3.3</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
 </table>
 
 </div>

docs/releasing.html

@@ -96,7 +96,7 @@ described in the same section.
 
 <p>
 Nomination happens in the mesa-stable@ mailing list. However,
-maintainer is responsible of checking for forgotten candidates in the
+maintainer is resposible of checking for forgotten candidates in the
 master branch. This is achieved by a combination of ad-hoc scripts and
 a casual search for terms such as regression, fix, broken and similar.
 </p>
@@ -272,11 +272,6 @@ It is followed by a brief period (normally 24 or 48 hours) before the actual
 release is made.
 </p>
 
-<p>
-Be aware to add a note to warn about a final release in a series, if
-that is the case.
-</p>
-
 <h2>Terminology used</h2>
 
 <ul><li>Nominated</ul>
@@ -316,10 +311,6 @@ The candidate for the Mesa X.Y.Z is now available. Currently we have:
  - NUMBER nominated (outstanding)
  - and NUMBER rejected patches
 
-[If applicable:
-Note: this is the final anticipated release in the SERIES series. Users are
-encouraged to migrate to the NEXT_SERIES series in order to obtain future fixes.]
-
 BRIEF SUMMARY OF CHANGES
 
 Take a look at section "Mesa stable queue" for more information.
@@ -383,9 +374,6 @@ Queued (NUMBER)
 
 AUTHOR (NUMBER):
       COMMIT SUMMARY
-[If applicable:
-Squashed with
-      COMMIT SUMMARY]
 
 For example:
 
@@ -394,21 +382,16 @@ Jonas Pfeil (1):
 Squashed with
       ralloc: don't leave out the alignment factor
 
-
 Rejected (NUMBER)
 =================
 
+Rejected (11)
+=============
+
 AUTHOR (NUMBER):
       SHA     COMMIT SUMMARY
 
 Reason: ...
-
-For example:
-
-Emil Velikov (1)
-      a39ad18 configure.ac: honour LLVM_LIBDIR when linking against LLVM
-
-Reason: The patch was reverted shortly after it was merged.
 </pre>
 
 
@@ -474,9 +457,9 @@ Here is one solution that I've been using.
 	cd .. &amp;&amp; rm -rf mesa-$__version
 
 	# Test the automake binaries
+	tar -xaf mesa-$__version.tar.xz &amp;&amp; cd mesa-$__version
 	# Restore LLVM_CONFIG, if applicable:
 	# export LLVM_CONFIG=`echo $save_LLVM_CONFIG`; unset save_LLVM_CONFIG
-	tar -xaf mesa-$__version.tar.xz &amp;&amp; cd mesa-$__version
 	./configure \
 		--with-dri-drivers=i965,swrast \
 		--with-gallium-drivers=swrast \
@@ -488,10 +471,6 @@ Here is one solution that I've been using.
 		--enable-egl \
 		--with-platforms=x11,drm,wayland,surfaceless
 	make &amp;&amp; DESTDIR=`pwd`/test make install
-
-	# Drop LLVM_CONFIG, if applicable:
-	# unset LLVM_CONFIG
-
 	__glxinfo_cmd='glxinfo 2>&amp;1 | egrep -o "Mesa.*|Gallium.*|.*dri\.so"'
 	__glxgears_cmd='glxgears 2>&amp;1 | grep -v "configuration file"'
 	__es2info_cmd='es2_info 2>&amp;1 | egrep "GL_VERSION|GL_RENDERER|.*dri\.so"'
@@ -521,10 +500,8 @@ Here is one solution that I've been using.
 	unset LIBGL_DRIVERS_PATH
 	unset LIBGL_DEBUG
 	unset LIBGL_ALWAYS_SOFTWARE
-	unset GALLIUM_DRIVER
 	export VK_ICD_FILENAMES=`pwd`/src/intel/vulkan/dev_icd.json
 	steam steam://rungameid/570  -vconsole -vulkan
-	unset VK_ICD_FILENAMES
 </pre>
 
 <h3>Update version in file VERSION</h3>
@@ -603,8 +580,7 @@ Something like the following steps will do the trick:
 
 <p>
 Also, edit docs/relnotes.html to add a link to the new release notes,
-edit docs/index.html to add a news entry and a note in case of the
-last release in a series, and remove the version from
+edit docs/index.html to add a news entry, and remove the version from
 docs/release-calendar.html. Then commit and push:
 </p>
 
@@ -620,11 +596,6 @@ docs/release-calendar.html. Then commit and push:
 Use the generated template during the releasing process.
 </p>
 
-<p>
-Again, pay attention to add a note to warn about a final release in a
-series, if that is the case.
-</p>
-
 
 <h1 id="website">Update the mesa3d.org website</h1>
 

docs/relnotes.html

@@ -21,15 +21,6 @@ The release notes summarize what's new or changed in each Mesa release.
 </p>
 
 <ul>
-<li><a href="relnotes/17.3.2.html">17.3.3 release notes</a>
-<li><a href="relnotes/17.3.2.html">17.3.2 release notes</a>
-<li><a href="relnotes/17.2.8.html">17.2.8 release notes</a>
-<li><a href="relnotes/17.3.1.html">17.3.1 release notes</a>
-<li><a href="relnotes/17.2.7.html">17.2.7 release notes</a>
-<li><a href="relnotes/17.3.0.html">17.3.0 release notes</a>
-<li><a href="relnotes/17.2.6.html">17.2.6 release notes</a>
-<li><a href="relnotes/17.2.5.html">17.2.5 release notes</a>
-<li><a href="relnotes/17.2.4.html">17.2.4 release notes</a>
 <li><a href="relnotes/17.2.3.html">17.2.3 release notes</a>
 <li><a href="relnotes/17.2.2.html">17.2.2 release notes</a>
 <li><a href="relnotes/17.1.10.html">17.1.10 release notes</a>

docs/relnotes/17.2.4.html

@@ -1,132 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.2.4 Release Notes / October 30, 2017</h1>
-
-<p>
-Mesa 17.2.4 is a bug fix release which fixes bugs found since the 17.2.3 release.
-</p>
-<p>
-Mesa 17.2.4 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-cb266edc5cf7226219ebaf556ca2e03dff282e0324d20afd80423a5754d1272c  mesa-17.2.4.tar.gz
-5ba408fecd6e1132e5490eec1a2f04466214e4c65c8b89b331be844768c2e550  mesa-17.2.4.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102774">Bug 102774</a> - [BDW] [Bisected] Absolute constant buffers break VAAPI in mpv</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103388">Bug 103388</a> - Linking libcltgsi.la (llvm/codegen/libclllvm_la-common.lo) fails with &quot;error: no match for 'operator-'&quot; with GCC-7, Mesa from Git and current LLVM revisions</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-<p>Andres Gomez (8):</p>
-<ul>
-  <li>cherry-ignore: configure.ac: rework llvm detection and handling</li>
-  <li>cherry-ignore: glsl: fix derived cs variables</li>
-  <li>cherry-ignore: added 17.3 nominations.</li>
-  <li>cherry-ignore: radv: Don't use vgpr indexing for outputs on GFX9.</li>
-  <li>cherry-ignore: radv: Disallow indirect outputs for GS on GFX9 as well.</li>
-  <li>cherry-ignore: mesa/bufferobj: don't double negate the range</li>
-  <li>cherry-ignore: broadcom/vc5: Propagate vc4 aliasing fix to vc5.</li>
-  <li>Update version to 17.2.4</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (1):</p>
-<ul>
-  <li>ac/nir: Fix nir_texop_lod on GFX for 1D arrays.</li>
-</ul>
-
-<p>Dave Airlie (1):</p>
-<ul>
-  <li>radv/image: bump all the offset to uint64_t.</li>
-</ul>
-
-<p>Emil Velikov (1):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.2.3</li>
-</ul>
-
-<p>Henri Verbeet (1):</p>
-<ul>
-  <li>vulkan/wsi: Free the event in x11_manage_fifo_queues().</li>
-</ul>
-
-<p>Jan Vesely (1):</p>
-<ul>
-  <li>clover: Fix compilation after clang r315871</li>
-</ul>
-
-<p>Jason Ekstrand (4):</p>
-<ul>
-  <li>nir/intrinsics: Set the correct num_indices for load_output</li>
-  <li>intel/fs: Handle flag read/write aliasing in needs_src_copy</li>
-  <li>anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir</li>
-  <li>intel/eu: Use EXECUTE_1 for JMPI</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>i965: Revert absolute mode for constant buffer pointers.</li>
-</ul>
-
-<p>Marek Olšák (1):</p>
-<ul>
-  <li>Revert "mesa: fix texture updates for ATI_fragment_shader"</li>
-</ul>
-
-<p>Matthew Nicholls (1):</p>
-<ul>
-  <li>ac/nir: generate correct instruction for atomic min/max on unsigned images</li>
-</ul>
-
-<p>Michel Dänzer (1):</p>
-<ul>
-  <li>st/mesa: Initialize textures array in st_framebuffer_validate</li>
-</ul>
-
-<p>Samuel Pitoiset (1):</p>
-<ul>
-  <li>radv: add the draw count buffer to the list of buffers</li>
-</ul>
-
-<p>Stefan Schake (1):</p>
-<ul>
-  <li>broadcom/vc4: Fix aliasing issue</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.2.5.html

@@ -1,156 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.2.5 Release Notes / November 10, 2017</h1>
-
-<p>
-Mesa 17.2.5 is a bug fix release which fixes bugs found since the 17.2.4 release.
-</p>
-<p>
-Mesa 17.2.5 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-25b40e72fad64b096c2d8d6fe9579369954debe7970d4ad53e5033c7eec2918b  mesa-17.2.5.tar.gz
-7f7f914b7b9ea0b15f2d9d01a4375e311b0e90e55683b8e8a67ce8691eb1070f  mesa-17.2.5.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97532">Bug 97532</a> - Regression: GLB 2.7 &amp; Glmark-2 GLES versions segfault due to linker precision error (259fc505) on dead variable</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102680">Bug 102680</a> - [OpenGL CTS] KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102809">Bug 102809</a> - Rust shadows(?) flash random colours</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103142">Bug 103142</a> - R600g+sb: optimizer apparently stuck in an endless loop</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-<p>Andres Gomez (8):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.2.4</li>
-  <li>cherry-ignore: radv: copy indirect lowering settings from radeonsi</li>
-  <li>cherry-ignore: i965: fix blorp stage_prog_data-&gt;param leak</li>
-  <li>cherry-ignore: etnaviv: don't do resolve-in-place without valid TS</li>
-  <li>cherry-ignore: intel/fs: Alloc pull constants off mem_ctx</li>
-  <li>cherry-ignore: added 17.3 nominations.</li>
-  <li>cherry-ignore: automake: include git_sha1.h.in in release tarball</li>
-  <li>Update version to 17.2.5</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (3):</p>
-<ul>
-  <li>radv: Don't expose heaps with 0 memory.</li>
-  <li>radv: Don't use vgpr indexing for outputs on GFX9.</li>
-  <li>radv: Disallow indirect outputs for GS on GFX9 as well.</li>
-</ul>
-
-<p>Dave Airlie (3):</p>
-<ul>
-  <li>i915g: make gears run again.</li>
-  <li>radv: free attachments on end command buffer.</li>
-  <li>radv: add initial copy descriptor support. (v2)</li>
-</ul>
-
-<p>Eric Engestrom (1):</p>
-<ul>
-  <li>vc4: fix release build</li>
-</ul>
-
-<p>Gert Wollny (1):</p>
-<ul>
-  <li>r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling</li>
-</ul>
-
-<p>Jason Ekstrand (4):</p>
-<ul>
-  <li>spirv: Claim support for the simple memory model</li>
-  <li>i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees</li>
-  <li>i965/blorp: Use more temporary isl_format variables</li>
-  <li>i965/miptree: Take an isl_format in render_aux_usage</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.</li>
-</ul>
-
-<p>Leo Liu (1):</p>
-<ul>
-  <li>radeon/video: add gfx9 offsets when rejoin the video surface</li>
-</ul>
-
-<p>Marek Olšák (2):</p>
-<ul>
-  <li>st/dri: don't expose modifiers in EGL if the driver doesn't implement them</li>
-  <li>ac/surface/gfx9: don't allow DCC for the smallest mipmap levels</li>
-</ul>
-
-<p>Nanley Chery (1):</p>
-<ul>
-  <li>i965: Check CCS_E compatibility for texture view rendering</li>
-</ul>
-
-<p>Neil Roberts (1):</p>
-<ul>
-  <li>nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB</li>
-</ul>
-
-<p>Nicolai Hähnle (1):</p>
-<ul>
-  <li>amd/common/gfx9: workaround DCC corruption more conservatively</li>
-</ul>
-
-<p>Tapani Pälli (1):</p>
-<ul>
-  <li>i965: unref push_const_bo in intelDestroyContext</li>
-</ul>
-
-<p>Timothy Arceri (1):</p>
-<ul>
-  <li>radv: copy indirect lowering settings from radeonsi</li>
-</ul>
-
-<p>Tomasz Figa (1):</p>
-<ul>
-  <li>glsl: Allow precision mismatch on dead data with GLSL ES 1.00</li>
-</ul>
-
-<p>Topi Pohjolainen (1):</p>
-<ul>
-  <li>intel/compiler/gen9: Pixel shader header only workaround</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.2.6.html

@@ -1,187 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.2.6 Release Notes / November 25, 2017</h1>
-
-<p>
-Mesa 17.2.6 is a bug fix release which fixes bugs found since the 17.2.5 release.
-</p>
-<p>
-Mesa 17.2.6 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-a9ed76702ffb14ad674ad48899f5c8c7e3a0f987911878a5dfdc4117dce5b415  mesa-17.2.6.tar.gz
-6ad85224620330be26ab68c8fc78381b12b38b610ade2db8716b38faaa8f30de  mesa-17.2.6.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100438">Bug 100438</a> - glsl/ir.cpp:1376: ir_dereference_variable::ir_dereference_variable(ir_variable*): Assertion `var != NULL' failed.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102177">Bug 102177</a> - [SKL] ES31-CTS.core.sepshaderobjs.StateInteraction fails sporadically</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103115">Bug 103115</a> - [BSW BXT GLK] dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103519">Bug 103519</a> - wayland egl apps crash on start with mesa 17.2</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103529">Bug 103529</a> - [GM45] GPU hang with mpv fullscreen (bisected)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103628">Bug 103628</a> - [BXT, GLK, BSW] KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103787">Bug 103787</a> - [BDW,BSW] gpu hang on spec.arb_pipeline_statistics_query.arb_pipeline_statistics_query-comp</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-<p>Adam Jackson (2):</p>
-<ul>
-  <li>glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)</li>
-  <li>glx/dri3: Fix passing renderType into glXCreateContext</li>
-</ul>
-
-<p>Alex Smith (2):</p>
-<ul>
-  <li>spirv: Use correct type for sampled images</li>
-  <li>nir/spirv: tg4 requires a sampler</li>
-</ul>
-
-<p>Andres Gomez (14):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.2.5</li>
-  <li>cherry-ignore: intel/fs: Use a pure vertical stride for large register strides</li>
-  <li>cherry-ignore: intel/nir: Use the correct indirect lowering masks in link_shaders</li>
-  <li>cherry-ignore: intel/fs: Use the original destination region for int MUL lowering</li>
-  <li>cherry-ignore: intel/fs: refactors</li>
-  <li>cherry-ignore: r600/shader: reserve first register of vertex shader.</li>
-  <li>cherry-ignore: anv/cmd_buffer: Advance the address when initializing clear colors</li>
-  <li>cherry-ignore: anv/cmd_buffer: Take bo_offset into account in fast clear state addresses</li>
-  <li>cherry-ignore: i965: Mark BOs as external when we export their handle</li>
-  <li>cherry-ignore: added 17.3 nominations.</li>
-  <li>cherry-ignore: glsl: Fix typo fragement -&gt; fragment</li>
-  <li>cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions</li>
-  <li>cherry-ignore: Revert "intel/fs: Use a pure vertical stride for large register strides"</li>
-  <li>Update version to 17.2.6</li>
-</ul>
-
-<p>Anuj Phogat (2):</p>
-<ul>
-  <li>i965: Program DWord Length in MI_FLUSH_DW</li>
-  <li>i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (2):</p>
-<ul>
-  <li>radv: Free syncobj with multiple imports.</li>
-  <li>radv: Free temporary syncobj after waiting on it.</li>
-</ul>
-
-<p>Dave Airlie (1):</p>
-<ul>
-  <li>r600: fix isoline tess factor component swapping.</li>
-</ul>
-
-<p>Derek Foreman (1):</p>
-<ul>
-  <li>egl/wayland: Add a fallback when fourcc query isn't supported</li>
-</ul>
-
-<p>Dylan Baker (1):</p>
-<ul>
-  <li>autotools: Set C++ visibility flags on Intel</li>
-</ul>
-
-<p>Emil Velikov (3):</p>
-<ul>
-  <li>targets/opencl: don't hardcode the icd file install to /etc/...</li>
-  <li>configure.ac: loosen --enable-glvnd check to honour egl</li>
-  <li>configure.ac: require xcb* for the omx/va/... when using x11 platform</li>
-</ul>
-
-<p>George Barrett (1):</p>
-<ul>
-  <li>glsl: Catch subscripted calls to undeclared subroutines</li>
-</ul>
-
-<p>Jason Ekstrand (9):</p>
-<ul>
-  <li>intel/fs: Use ANY/ALL32 predicates in SIMD32</li>
-  <li>intel/fs: Use an explicit D type for vote any/all/eq intrinsics</li>
-  <li>intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all</li>
-  <li>intel/eu/reg: Add a subscript() helper</li>
-  <li>intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core</li>
-  <li>intel/fs: Fix integer multiplication lowering for src/dst hazards</li>
-  <li>intel/fs: Mark 64-bit values as being contiguous</li>
-  <li>intel/fs: Rework zero-length URB write handling</li>
-  <li>i965: Add stencil buffers to cache set regardless of stencil texturing</li>
-</ul>
-
-<p>Kenneth Graunke (5):</p>
-<ul>
-  <li>i965: properly initialize brw-&gt;cs.base.stage to MESA_SHADER_COMPUTE</li>
-  <li>i965: Make L3 configuration atom listen for TCS/TES program updates.</li>
-  <li>intel/tools: Fix detection of enabled shader stages.</li>
-  <li>i965: Implement another VF cache invalidate workaround on Gen8+.</li>
-  <li>i965: Upload invariant state once at the start of the batch on Gen4-5.</li>
-</ul>
-
-<p>Matt Turner (2):</p>
-<ul>
-  <li>i965/fs: Fix extract_i8/u8 to a 64-bit destination</li>
-  <li>i965/fs: Split all 32-&gt;64-bit MOVs on CHV, BXT, GLK</li>
-</ul>
-
-<p>Neil Roberts (1):</p>
-<ul>
-  <li>glsl: Transform fb buffers are only active if a variable uses them</li>
-</ul>
-
-<p>Nicolai Hähnle (1):</p>
-<ul>
-  <li>ddebug: fix use-after-free of streamout targets</li>
-</ul>
-
-<p>Tim Rowley (2):</p>
-<ul>
-  <li>swr/rast: Use gather instruction for i32gather_ps on simd16/avx512</li>
-  <li>swr/rast: Faster emulated simd16 permute</li>
-</ul>
-
-<p>Timothy Arceri (3):</p>
-<ul>
-  <li>glsl: drop cache_fallback</li>
-  <li>glsl: use the correct parent when allocating program data members</li>
-  <li>mesa: rework how we free gl_shader_program_data</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.2.7.html

@@ -1,247 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.2.7 Release Notes / December 14, 2017</h1>
-
-<p>
-Mesa 17.2.7 is a bug fix release which fixes bugs found since the 17.2.6 release.
-</p>
-<p>
-Mesa 17.2.7 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-e8d837a1cd55014e636e9caf6c75cfbe1b3e4be9ab3fa125f5ef38398aa12e97  mesa-17.2.7.tar.gz
-50cfdea8df55045797b4d0409591c04c784d9551c4da09b8178874dbe5a37a68  mesa-17.2.7.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=94739">Bug 94739</a> - Mesa 11.1.2 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in _mesa_unpack_uint_24_8_depth_stencil_row</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101378">Bug 101378</a> - interpolateAtSample check for input parameter is too strict</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102006">Bug 102006</a> - gstreamer vaapih264enc segfault</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102435">Bug 102435</a> - [skl,kbl] [drm] GPU HANG: ecode 9:0:0x86df7cf9, in csgo_linux64 [4947], reason: Hang on rcs, action: reset</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102552">Bug 102552</a> - Null dereference due to not checking return value of util_format_description</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102677">Bug 102677</a> - [OpenGL CTS] KHR-GL45.CommonBugs.CommonBug_PerVertexValidation fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103098">Bug 103098</a> - [OpenGL CTS] KHR-GL45.enhanced_layouts.varying_structure_locations fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103227">Bug 103227</a> - [G965 G45 ILK] ES2-CTS.gtf.GL2ExtensionTests.texture_float.texture_float regression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103393">Bug 103393</a> - glDispatchComputeGroupSizeARB : gl_GlobalInvocationID.x != gl_WorkGroupID.x * gl_LocalGroupSizeARB.x + gl_LocalInvocationID.x</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103412">Bug 103412</a> - gallium/wgl: Another fix to context creation without prior SetPixelFormat()</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103616">Bug 103616</a> - Increased difference from reference image in shaders</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103626">Bug 103626</a> - [SNB] ES3-CTS.functional.shaders.precision</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103732">Bug 103732</a> - [swr] often gets stuck in piglit's glx-multi-context-single-window test</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103909">Bug 103909</a> - anv_allocator.c:113:1: error: static declaration of ‘memfd_create’ follows non-static declaration</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103966">Bug 103966</a> - Mesa 17.2.5 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in _mesa_unpack_uint_24_8_depth_stencil_row</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104119">Bug 104119</a> - radv: OpBitFieldInsert produces 0 with a loop counter for Insert</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104143">Bug 104143</a> - r600/sb: clobbers gl_Position -&gt; gl_FragCoord</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Alex Smith (1):</p>
-<ul>
-  <li>radv: Add LLVM version to the device name string</li>
-</ul>
-
-<p>Andres Gomez (2):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.2.6</li>
-  <li>docs: remove bug 103626 from fix list as per 17.2.6</li>
-</ul>
-
-<p>Ben Crocker (2):</p>
-<ul>
-  <li>docs/llvmpipe.html: Minor edits</li>
-  <li>docs/llvmpipe: document ppc64le as alternative architecture to x86.</li>
-</ul>
-
-<p>Dave Airlie (1):</p>
-<ul>
-  <li>r600/sb: handle jump after target to end of program. (v2)</li>
-</ul>
-
-<p>Denis Pauk (1):</p>
-<ul>
-  <li>gallium/{r600, radeonsi}: Fix segfault with color format (v2)</li>
-</ul>
-
-<p>Eduardo Lima Mitev (3):</p>
-<ul>
-  <li>glsl_parser_extra: Add utility to copy symbols between symbol tables</li>
-  <li>glsl: Use the utility function to copy symbols between symbol tables</li>
-  <li>glsl/linker: Check that re-declared, inter-shader built-in blocks match</li>
-</ul>
-
-<p>Emil Velikov (3):</p>
-<ul>
-  <li>gl_table.py: add extern C guard for the generated glapitable.h</li>
-  <li>cherry-ignore: radeonsi: allow DMABUF exports for local buffers</li>
-  <li>Update version to 17.2.7</li>
-</ul>
-
-<p>Eric Anholt (1):</p>
-<ul>
-  <li>broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.</li>
-</ul>
-
-<p>Eric Engestrom (1):</p>
-<ul>
-  <li>compiler: use NDEBUG to guard asserts</li>
-</ul>
-
-<p>Fabian Bieler (2):</p>
-<ul>
-  <li>glsl: Match order of gl_LightSourceParameters elements.</li>
-  <li>glsl: Fix gl_NormalScale.</li>
-</ul>
-
-<p>Frank Richter (1):</p>
-<ul>
-  <li>gallium/wgl: fix default pixel format issue</li>
-</ul>
-
-<p>George Kyriazis (1):</p>
-<ul>
-  <li>swr: Handle resource across context changes</li>
-</ul>
-
-<p>Gert Wollny (2):</p>
-<ul>
-  <li>r600: Emit EOP for more CF instruction types</li>
-  <li>r600/sb: do not convert if-blocks that contain indirect array access</li>
-</ul>
-
-<p>Ilia Mirkin (1):</p>
-<ul>
-  <li>glsl: fix derived cs variables</li>
-</ul>
-
-<p>James Legg (1):</p>
-<ul>
-  <li>nir/opcodes: Fix constant-folding of bitfield_insert</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>i965: Disable regular fast-clears (CCS_D) on gen9+</li>
-</ul>
-
-<p>Juan A. Suarez Romero (1):</p>
-<ul>
-  <li>glsl: add varying resources for arrays of complex types</li>
-</ul>
-
-<p>Julien Isorce (1):</p>
-<ul>
-  <li>st/va: change frame_idx from array to hash table</li>
-</ul>
-
-<p>Kai Wasserbäch (1):</p>
-<ul>
-  <li>docs: Point to apt.llvm.org for development snapshot packages</li>
-</ul>
-
-<p>Kenneth Graunke (3):</p>
-<ul>
-  <li>meta: Initialize depth/clear values on declaration.</li>
-  <li>meta: Fix ClearTexture with GL_DEPTH_COMPONENT.</li>
-  <li>i965: Fix Smooth Point Enables.</li>
-</ul>
-
-<p>Marek Olšák (3):</p>
-<ul>
-  <li>radeonsi: fix layered DCC fast clear</li>
-  <li>radeonsi/gfx9: fix importing shared textures with DCC</li>
-  <li>radeonsi: flush the context after resource_copy_region for buffer exports</li>
-</ul>
-
-<p>Matt Turner (4):</p>
-<ul>
-  <li>i965/fs: Handle negating immediates on MADs when propagating saturates</li>
-  <li>util: Fix SHA1 implementation on big endian</li>
-  <li>util: Fix disk_cache index calculation on big endian</li>
-  <li>i965/fs: Unpack count argument to 64-bit shift ops on Atom</li>
-</ul>
-
-<p>Nicolai Hähnle (3):</p>
-<ul>
-  <li>radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check</li>
-  <li>glsl: allow any l-value of an input variable as interpolant in interpolateAt*</li>
-  <li>glsl: fix interpolateAtXxx(some_vec[idx], ...) with dynamic idx</li>
-</ul>
-
-<p>Pierre Moreau (1):</p>
-<ul>
-  <li>nvc0/ir: Properly lower 64-bit shifts when the shift value is &gt;32</li>
-</ul>
-
-<p>Tapani Pälli (1):</p>
-<ul>
-  <li>mesa/gles: adjust internal format in glTexSubImage2D error checks</li>
-</ul>
-
-<p>Timothy Arceri (1):</p>
-<ul>
-  <li>glsl: get correct member type when processing xfb ifc arrays</li>
-</ul>
-
-<p>Vadym Shovkoplias (2):</p>
-<ul>
-  <li>intel/blorp: Fix possible NULL pointer dereferencing</li>
-  <li>glx/dri3: Remove unused deviceName variable</li>
-</ul>
-
-<p>Vinson Lee (1):</p>
-<ul>
-  <li>anv: Check if memfd_create is already defined.</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.2.8.html

@@ -1,112 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.2.8 Release Notes / December 22, 2017</h1>
-
-<p>
-Mesa 17.2.8 is a bug fix release which fixes bugs found since the 17.2.7 release.
-</p>
-<p>
-Mesa 17.2.8 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-c715c3a3d6fe26a69c096f573ec416e038a548f0405e3befedd5136517527a84  mesa-17.2.8.tar.gz
-6e940345cceaadfd805d701ed2b956589fa77fe8c39991da30ed51ea6b9d095f  mesa-17.2.8.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102710">Bug 102710</a> - vkCmdBlitImage with arrayLayers &gt; 1 fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103007">Bug 103007</a> - [OpenGL CTS] [HSW] KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103544">Bug 103544</a> - Graphical glitches r600 in game this war of mine linux native</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103579">Bug 103579</a> - Vertex shader causes compiler to crash in SPIRV-to-NIR</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andres Gomez (6):</p>
-<ul>
-  <li>cherry-ignore: swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.</li>
-  <li>cherry-ignore: added 17.3 nominations.</li>
-  <li>cherry-ignore: radv: port merge tess info from anv</li>
-  <li>cherry-ignore: main: Clear shader program data whenever ProgramBinary is called</li>
-  <li>cherry-ignore: r600: set DX10_CLAMP for compute shader too</li>
-  <li>Update version to 17.2.8</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (2):</p>
-<ul>
-  <li>spirv: Fix loading an entire block at once.</li>
-  <li>radv: Fix multi-layer blits.</li>
-</ul>
-
-<p>Brian Paul (2):</p>
-<ul>
-  <li>xlib: call _mesa_warning() instead of fprintf()</li>
-  <li>gallium/aux: include nr_samples in util_resource_size() computation</li>
-</ul>
-
-<p>Emil Velikov (1):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.2.7</li>
-</ul>
-
-<p>Iago Toral Quiroga (1):</p>
-<ul>
-  <li>i965/vec4: use a temp register to compute offsets for pull loads</li>
-</ul>
-
-<p>Leo Liu (1):</p>
-<ul>
-  <li>radeon/vce: move destroy command before feedback command</li>
-</ul>
-
-<p>Matt Turner (2):</p>
-<ul>
-  <li>util: Assume little endian in the absence of platform-specific handling</li>
-  <li>util: Add a SHA1 unit test program</li>
-</ul>
-
-<p>Roland Scheidegger (2):</p>
-<ul>
-  <li>r600: use min_dx10/max_dx10 instead of min/max</li>
-  <li>r600: use DX10_CLAMP bit in shader setup</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.3.0.html

@@ -33,8 +33,7 @@ because compatibility contexts are not supported.
 
 <h2>SHA256 checksums</h2>
 <pre>
-0cb1ffe2b4637d80f08df3bdfeb300352dcffd8ff4f6711278639b084e3f07f9  mesa-17.3.0.tar.gz
-29a0a3a6c39990d491a1a58ed5c692e596b3bfc6c01d0b45e0b787116c50c6d9  mesa-17.3.0.tar.xz
+TBD.
 </pre>
 
 

docs/relnotes/17.3.1.html

@@ -1,191 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.1 Release Notes / December 21, 2017</h1>
-
-<p>
-Mesa 17.3.1 is a bug fix release which fixes bugs found since the 17.3.0 release.
-</p>
-<p>
-Mesa 17.3.1 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-b0bb0419dbe3043ed4682a28eaf95721f427ca3f23a3c2a7dc77dbe8a3b6384d  mesa-17.3.1.tar.gz
-9ae607e0998a586fb2c866cfc8e45e6f52d1c56cb1b41288253ea83eada824c1  mesa-17.3.1.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=94739">Bug 94739</a> - Mesa 11.1.2 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in _mesa_unpack_uint_24_8_depth_stencil_row</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102710">Bug 102710</a> - vkCmdBlitImage with arrayLayers &gt; 1 fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103579">Bug 103579</a> - Vertex shader causes compiler to crash in SPIRV-to-NIR</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103966">Bug 103966</a> - Mesa 17.2.5 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in _mesa_unpack_uint_24_8_depth_stencil_row</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104119">Bug 104119</a> - radv: OpBitFieldInsert produces 0 with a loop counter for Insert</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104143">Bug 104143</a> - r600/sb: clobbers gl_Position -&gt; gl_FragCoord</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Alex Smith (1):</p>
-<ul>
-  <li>radv: Add LLVM version to the device name string</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (3):</p>
-<ul>
-  <li>spirv: Fix loading an entire block at once.</li>
-  <li>radv: Don't advertise VK_EXT_debug_report.</li>
-  <li>radv: Fix multi-layer blits.</li>
-</ul>
-
-<p>Ben Crocker (1):</p>
-<ul>
-  <li>docs/llvmpipe: document ppc64le as alternative architecture to x86.</li>
-</ul>
-
-<p>Brian Paul (2):</p>
-<ul>
-  <li>xlib: call _mesa_warning() instead of fprintf()</li>
-  <li>gallium/aux: include nr_samples in util_resource_size() computation</li>
-</ul>
-
-<p>Bruce Cherniak (1):</p>
-<ul>
-  <li>swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.</li>
-</ul>
-
-<p>Dave Airlie (1):</p>
-<ul>
-  <li>radv: port merge tess info from anv</li>
-</ul>
-
-<p>Emil Velikov (5):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.0</li>
-  <li>util: scons: wire up the sha1 test</li>
-  <li>cherry-ignore: meson: fix strtof locale support check</li>
-  <li>cherry-ignore: util: add mesa-sha1 test to meson</li>
-  <li>Update version to 17.3.1</li>
-</ul>
-
-<p>Eric Anholt (1):</p>
-<ul>
-  <li>broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.</li>
-</ul>
-
-<p>Eric Engestrom (1):</p>
-<ul>
-  <li>compiler: use NDEBUG to guard asserts</li>
-</ul>
-
-<p>Fabian Bieler (2):</p>
-<ul>
-  <li>glsl: Match order of gl_LightSourceParameters elements.</li>
-  <li>glsl: Fix gl_NormalScale.</li>
-</ul>
-
-<p>Gert Wollny (1):</p>
-<ul>
-  <li>r600/sb: do not convert if-blocks that contain indirect array access</li>
-</ul>
-
-<p>James Legg (1):</p>
-<ul>
-  <li>nir/opcodes: Fix constant-folding of bitfield_insert</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>i965: Switch over to fully external-or-not MOCS scheme</li>
-</ul>
-
-<p>Juan A. Suarez Romero (1):</p>
-<ul>
-  <li>travis: disable Meson build</li>
-</ul>
-
-<p>Kenneth Graunke (2):</p>
-<ul>
-  <li>meta: Initialize depth/clear values on declaration.</li>
-  <li>meta: Fix ClearTexture with GL_DEPTH_COMPONENT.</li>
-</ul>
-
-<p>Leo Liu (1):</p>
-<ul>
-  <li>radeon/vce: move destroy command before feedback command</li>
-</ul>
-
-<p>Marek Olšák (4):</p>
-<ul>
-  <li>radeonsi: flush the context after resource_copy_region for buffer exports</li>
-  <li>radeonsi: allow DMABUF exports for local buffers</li>
-  <li>winsys/amdgpu: disable local BOs again due to worse performance</li>
-  <li>radeonsi: don't call force_dcc_off for buffers</li>
-</ul>
-
-<p>Matt Turner (2):</p>
-<ul>
-  <li>util: Assume little endian in the absence of platform-specific handling</li>
-  <li>util: Add a SHA1 unit test program</li>
-</ul>
-
-<p>Nicolai Hähnle (1):</p>
-<ul>
-  <li>radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check</li>
-</ul>
-
-<p>Pierre Moreau (1):</p>
-<ul>
-  <li>nvc0/ir: Properly lower 64-bit shifts when the shift value is &gt;32</li>
-</ul>
-
-<p>Timothy Arceri (1):</p>
-<ul>
-  <li>glsl: get correct member type when processing xfb ifc arrays</li>
-</ul>
-
-<p>Vadym Shovkoplias (2):</p>
-<ul>
-  <li>glx/dri3: Remove unused deviceName variable</li>
-  <li>util/disk_cache: Remove unneeded free() on always null string</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.3.2.html

@@ -1,109 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.2 Release Notes / January 8, 2018</h1>
-
-<p>
-Mesa 17.3.2 is a bug fix release which fixes bugs found since the 17.3.1 release.
-</p>
-<p>
-Mesa 17.3.2 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-f997e80f14c385f9a2ba827c2b74aebf1b7426712ca4a81c631ef9f78e437bf4  mesa-17.3.2.tar.gz
-e2844a13f2d6f8f24bee65804a51c42d8dc6ae9c36cff7ee61d0940e796d64c6  mesa-17.3.2.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97852">Bug 97852</a> - Unreal Engine corrupted preview viewport</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103801">Bug 103801</a> - [i965] &gt;Observer_ issue</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104288">Bug 104288</a> - Steamroll needs allow_glsl_cross_stage_interpolation_mismatch=true</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Bas Nieuwenhuizen (1):</p>
-<ul>
-  <li>radv: Fix DCC compatible formats.</li>
-</ul>
-
-<p>Brendan King (1):</p>
-<ul>
-  <li>egl: link libEGL against the dynamic version of libglapi</li>
-</ul>
-
-<p>Dave Airlie (6):</p>
-<ul>
-  <li>radv/gfx9: add support for 3d images to blit 2d paths</li>
-  <li>radv: handle depth/stencil image copy with layouts better. (v3.1)</li>
-  <li>radv/meta: fix blit paths for depth/stencil (v2.1)</li>
-  <li>radv: fix issue with multisample positions and interp_var_at_sample.</li>
-  <li>radv/gfx9: add 3d sampler image-&gt;buffer copy shader. (v3)</li>
-  <li>radv: don't do format replacement on tc compat htile surfaces.</li>
-</ul>
-
-<p>Emil Velikov (2):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.1</li>
-  <li>Update version to 17.3.2</li>
-</ul>
-
-<p>Eric Engestrom (1):</p>
-<ul>
-  <li>egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE</li>
-</ul>
-
-<p>Rob Herring (1):</p>
-<ul>
-  <li>egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameter</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>radv/gfx9: fix primitive topology when adjacency is used</li>
-  <li>radv: use a faster version for nir_op_pack_half_2x16</li>
-</ul>
-
-<p>Tapani Pälli (2):</p>
-<ul>
-  <li>mesa: add AllowGLSLCrossStageInterpolationMismatch workaround</li>
-  <li>drirc: set allow_glsl_cross_stage_interpolation_mismatch for more games</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.3.3.html

@@ -1,151 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.3 Release Notes / January 18, 2018</h1>
-
-<p>
-Mesa 17.3.3 is a bug fix release which fixes bugs found since the 17.3.2 release.
-</p>
-<p>
-Mesa 17.3.3 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-c733d37a161501cd81dc9b309ccb613753b98eafc6d35e0847548a6642749772  mesa-17.3.3.tar.gz
-41bac5de0ef6adc1f41a1ec0f80c19e361298ce02fa81b5f9ba4fdca33a9379b  mesa-17.3.3.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104214">Bug 104214</a> - Dota crashes when switching from game to desktop</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104492">Bug 104492</a> - Compute Shader: Wrong alignment when assigning struct value to structured SSBO</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104551">Bug 104551</a> - Check if Mako templates for Python are installed</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Alex Smith (3):</p>
-<ul>
-  <li>anv: Add missing unlock in anv_scratch_pool_alloc</li>
-  <li>anv: Take write mask into account in has_color_buffer_write_enabled</li>
-  <li>anv: Make sure state on primary is correct after CmdExecuteCommands</li>
-</ul>
-
-<p>Andres Gomez (1):</p>
-<ul>
-  <li>anv: Import mako templates only during execution of anv_extensions</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (11):</p>
-<ul>
-  <li>radv: Invert condition for all samples identical during resolve.</li>
-  <li>radv: Flush caches before subpass resolve.</li>
-  <li>radv: Fix fragment resolve destination offset.</li>
-  <li>radv: Use correct framebuffer size for partial FS resolves.</li>
-  <li>radv: Always use fragment resolve if dest uses DCC.</li>
-  <li>Revert "radv/gfx9: fix block compression texture views."</li>
-  <li>radv: Use correct HTILE expanded words.</li>
-  <li>radv: Allow writing 0 scissors.</li>
-  <li>ac/nir: Handle loading data from compact arrays.</li>
-  <li>radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.</li>
-  <li>ac/nir: Sanitize location_frac for local variables.</li>
-</ul>
-
-<p>Dave Airlie (8):</p>
-<ul>
-  <li>radv: fix events on compute queues.</li>
-  <li>radv: fix pipeline statistics end query on compute queue</li>
-  <li>radv/gfx9: fix 3d image to image transfers on compute queues.</li>
-  <li>radv/gfx9: fix 3d image clears on compute queues</li>
-  <li>radv/gfx9: fix buffer to image for 3d images on compute queues</li>
-  <li>radv/gfx9: fix block compression texture views.</li>
-  <li>radv/gfx9: use a bigger hammer to flush cb/db caches.</li>
-  <li>radv/gfx9: use correct swizzle parameter to work out border swizzle.</li>
-</ul>
-
-<p>Emil Velikov (1):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.2</li>
-</ul>
-
-<p>Florian Will (1):</p>
-<ul>
-  <li>glsl: Respect std430 layout in lower_buffer_access</li>
-</ul>
-
-<p>Juan A. Suarez Romero (6):</p>
-<ul>
-  <li>cherry-ignore: intel/fs: Use the original destination region for int MUL lowering</li>
-  <li>cherry-ignore: i965/fs: Use UW types when using V immediates</li>
-  <li>cherry-ignore: main: Clear shader program data whenever ProgramBinary is called</li>
-  <li>cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions</li>
-  <li>cherry-ignore: vulkan/wsi: free cmd pools</li>
-  <li>Update version to 17.3.3</li>
-</ul>
-
-<p>Józef Kucia (1):</p>
-<ul>
-  <li>radeonsi: fix alpha-to-coverage if color writes are disabled</li>
-</ul>
-
-<p>Kenneth Graunke (2):</p>
-<ul>
-  <li>i965: Require space for MI_BATCHBUFFER_END.</li>
-  <li>i965: Torch public intel_batchbuffer_emit_dword/float helpers.</li>
-</ul>
-
-<p>Lucas Stach (1):</p>
-<ul>
-  <li>etnaviv: disable in-place resolve for non-supertiled surfaces</li>
-</ul>
-
-<p>Samuel Iglesias Gonsálvez (1):</p>
-<ul>
-  <li>anv: VkDescriptorSetLayoutBinding can have descriptorCount == 0</li>
-</ul>
-
-<p>Thomas Hellstrom (1):</p>
-<ul>
-  <li>loader/dri3: Avoid freeing renderbuffers in use</li>
-</ul>
-
-<p>Tim Rowley (1):</p>
-<ul>
-  <li>swr/rast: fix invalid sign masks in avx512 simdlib code</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.0.html

@@ -1,321 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.0 Release Notes / March 27 2018</h1>
-
-<p>
-Mesa 18.0.0 is a new development release.
-People who are concerned with stability and reliability should stick
-with a previous release or wait for Mesa 18.0.1.
-</p>
-<p>
-Mesa 18.0.0 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-93c2d3504b2871ac2146603fb1270f341d36a39695e2950a469c5eac74f98457  mesa-18.0.0.tar.gz
-694e5c3d37717d23258c1f88bc134223c5d1aac70518d2f9134d6df3ee791eea  mesa-18.0.0.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-
-<p>
-Note: some of the new features are only available with certain drivers.
-</p>
-
-<ul>
-<li>Disk shader cache support for i965 when MESA_GLSL_CACHE_DISABLE environment variable is set to "0" or "false"</li>
-<li>GL_ARB_shader_atomic_counters and GL_ARB_shader_atomic_counter_ops on r600/evergreen+</li>
-<li>GL_ARB_shader_image_load_store and GL_ARB_shader_image_size on r600/evergreen+</li>
-<li>GL_ARB_shader_storage_buffer_object on r600/evergreen+<li>
-<li>GL_ARB_compute_shader on r600/evergreen+<li>
-<li>GL_ARB_cull_distance on r600/evergreen+</li>
-<li>GL_ARB_enhanced_layouts on r600/evergreen+</li>
-<li>GL_ARB_bindless_texture on nvc0/kepler</li>
-<li>OpenGL 4.3 on r600/evergreen with hw fp64 support</li>
-<li>Support 1 binary format for GL_ARB_get_program_binary on i965.
-    (For the 18.0 release, 0 formats continue to be supported in
-    compatibility profiles.)</li>
-<li>Cannonlake support on i965 and anv</li>
-</ul>
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85564">Bug 85564</a> - Dead Island rendering issues</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=90311">Bug 90311</a> - Fail to build libglx with clang at linking stage</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=92363">Bug 92363</a> - [BSW/BDW] ogles1conform Gets test fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=94739">Bug 94739</a> - Mesa 11.1.2 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in _mesa_unpack_uint_24_8_depth_stencil_row</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97532">Bug 97532</a> - Regression: GLB 2.7 &amp; Glmark-2 GLES versions segfault due to linker precision error (259fc505) on dead variable</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97852">Bug 97852</a> - Unreal Engine corrupted preview viewport</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100438">Bug 100438</a> - glsl/ir.cpp:1376: ir_dereference_variable::ir_dereference_variable(ir_variable*): Assertion `var != NULL' failed.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101378">Bug 101378</a> - interpolateAtSample check for input parameter is too strict</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101442">Bug 101442</a> - Piglit shaders&#64;ssa&#64;fs-if-def-else-break fails with sb but passes with R600_DEBUG=nosb</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101560">Bug 101560</a> - SPIR-V OpSwitch with int64 not supported even though shaderInt64 is true</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101691">Bug 101691</a> - gfx corruption on windowed 3d-apps running on dGPU</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102177">Bug 102177</a> - [SKL] ES31-CTS.core.sepshaderobjs.StateInteraction fails sporadically</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102264">Bug 102264</a> - Missing MESA_FORMAT_{B8G8R8A8,B8G8R8X8}_SRGB formats</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102354">Bug 102354</a> - Mesa 17.2 no longer can give SRGB-capable framebuffer on i965, even though Mesa 17.1.x does.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102358">Bug 102358</a> - WarThunder freezes at start, with activated vsync (vblank_mode=2)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102435">Bug 102435</a> - [skl,kbl] [drm] GPU hang in Valve games based on Source 1</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102503">Bug 102503</a> - Report SRGB framebuffer to SuperTuxKart to workaround SuperTuxKart crash</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102665">Bug 102665</a> - test_glsl_to_tgsi_lifetime.cpp:53:67: error: ‘&gt;&gt;’ should be ‘&gt; &gt;’ within a nested template argument list</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102677">Bug 102677</a> - [OpenGL CTS] KHR-GL45.CommonBugs.CommonBug_PerVertexValidation fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102680">Bug 102680</a> - [OpenGL CTS] KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102710">Bug 102710</a> - vkCmdBlitImage with arrayLayers &gt; 1 fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102774">Bug 102774</a> - [BDW] [Bisected] Absolute constant buffers break VAAPI in mpv</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102809">Bug 102809</a> - Rust shadows(?) flash random colours</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102897">Bug 102897</a> - Separate bind points are not implemented correctly</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102955">Bug 102955</a> - HyperZ related rendering issue in ARK: Survival Evolved</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103006">Bug 103006</a> - [OpenGL CTS] [HSW] KHR-GL45.vertex_attrib_binding.basic-inputL-case1</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103007">Bug 103007</a> - [OpenGL CTS] [HSW] KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103085">Bug 103085</a> - [ivb byt hsw] piglit.spec.arb_indirect_parameters.tf-count-arrays</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103098">Bug 103098</a> - [OpenGL CTS] KHR-GL45.enhanced_layouts.varying_structure_locations fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103101">Bug 103101</a> - [SKL][bisected] DiRT Rally GPU hang</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103115">Bug 103115</a> - [BSW BXT GLK] dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103128">Bug 103128</a> - [softpipe] piglit fs-ldexp regression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103142">Bug 103142</a> - R600g+sb: optimizer apparently stuck in an endless loop</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103227">Bug 103227</a> - [G965 G45 ILK] ES2-CTS.gtf.GL2ExtensionTests.texture_float.texture_float regression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103283">Bug 103283</a> - drm_get_device_name_for_fd is broken on FreeBSD</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103388">Bug 103388</a> - Linking libcltgsi.la (llvm/codegen/libclllvm_la-common.lo) fails with &quot;error: no match for 'operator-'&quot; with GCC-7, Mesa from Git and current LLVM revisions</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103393">Bug 103393</a> - glDispatchComputeGroupSizeARB : gl_GlobalInvocationID.x != gl_WorkGroupID.x * gl_LocalGroupSizeARB.x + gl_LocalInvocationID.x</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103412">Bug 103412</a> - gallium/wgl: Another fix to context creation without prior SetPixelFormat()</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103496">Bug 103496</a> - svga_screen.c:26:46: error: git_sha1.h: No such file or directory</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103513">Bug 103513</a> - [build failure] radv_shader.c:683:2: error: format not a string literal and no format arguments [-Werror=format-security]</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103519">Bug 103519</a> - wayland egl apps crash on start with mesa 17.2</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103529">Bug 103529</a> - [GM45] GPU hang with mpv fullscreen (bisected)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103537">Bug 103537</a> - i965: Shadow of Mordor broken since commit 379b24a40d3d34ffdaaeb1b328f50e28ecb01468 on Haswell</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103544">Bug 103544</a> - Graphical glitches r600 in game this war of mine linux native</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103579">Bug 103579</a> - Vertex shader causes compiler to crash in SPIRV-to-NIR</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103616">Bug 103616</a> - Increased difference from reference image in shaders</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103626">Bug 103626</a> - [SNB] ES3-CTS.functional.shaders.precision</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103628">Bug 103628</a> - [BXT, GLK, BSW] KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103653">Bug 103653</a> - Unreal segfault since gallium/u_threaded: avoid syncs for get_query_result</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103658">Bug 103658</a> - addrlib/gfx9/gfx9addrlib.cpp:727:50: error: expected expression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103674">Bug 103674</a> - u_queue.c:173:7: error: implicit declaration of function 'timespec_get' is invalid in C99</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103746">Bug 103746</a> - [BDW BSW SKL KBL] dEQP-GLES31.functional.copy_image regressions</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103759">Bug 103759</a> - plasma desktop corrupted rendering</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103784">Bug 103784</a> - [bisected] Egl changes breaks all of EGL</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103787">Bug 103787</a> - [BDW,BSW] gpu hang on spec.arb_pipeline_statistics_query.arb_pipeline_statistics_query-comp</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103801">Bug 103801</a> - [i965] &gt;Observer_ issue</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103808">Bug 103808</a> - [radeonsi, bisected] World of Warcraft scribbling all over screen</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103902">Bug 103902</a> - Portal 2 game  hangs at startup   with latest mesa dev</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103904">Bug 103904</a> - Source engine-based games won't hang at start without R600_DEBUG=vs</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103909">Bug 103909</a> - anv_allocator.c:113:1: error: static declaration of ‘memfd_create’ follows non-static declaration</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103942">Bug 103942</a> - KHR-GL46.enhanced_layouts.varying* regression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103955">Bug 103955</a> - Using array in structure results in wrong GLSL compilation output</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103966">Bug 103966</a> - Mesa 17.2.5 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in _mesa_unpack_uint_24_8_depth_stencil_row</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103988">Bug 103988</a> - Intermittent piglit failures with shader cache enabled</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104005">Bug 104005</a> - [sklgt4e] GPU hangs in Car_Chase</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104119">Bug 104119</a> - radv: OpBitFieldInsert produces 0 with a loop counter for Insert</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104141">Bug 104141</a> - include/c11/threads_posix.h:96: undefined reference to `pthread_once'</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104143">Bug 104143</a> - r600/sb: clobbers gl_Position -&gt; gl_FragCoord</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104163">Bug 104163</a> - [GEN9+] 2-3% perf drop in GfxBench Manhattan 3.1 from &quot;i965: Disable regular fast-clears (CCS_D) on gen9+&quot;</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104183">Bug 104183</a> - mesa-17.3.0/src/broadcom/qpu/qpu_pack.c:171]: (error) Invalid memcmp() argument</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104199">Bug 104199</a> - [i965 bisected] BIO and EM Vision in &gt;Observer_ is broken since commit af2c320190f3c73180f1610c8df955a7fa2a4d09</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104213">Bug 104213</a> - NULL pointer access crashes on compiling Vulkan compute shaders after &quot;anv: Add support for the variablePointers feature&quot;</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104214">Bug 104214</a> - Dota crashes when switching from game to desktop</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104226">Bug 104226</a> - [bisected] Anvil accesses uninitialized memory while compiling shaders</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104231">Bug 104231</a> - DispatchSanity_test.GL30 regression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104246">Bug 104246</a> - Talos Principle Vulkan version crash: spirv_to_nir() returns NULL entry_point</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104271">Bug 104271</a> - i965: Timeout in dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.5</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104288">Bug 104288</a> - Steamroll needs allow_glsl_cross_stage_interpolation_mismatch=true</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104302">Bug 104302</a> - Wolfenstein 2 (2017) under wine graphical artifacting on RADV</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104331">Bug 104331</a> - [r600g] Ogre demo &quot;TutorialUAV01&quot; crash at r600_decompress_color_images</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104338">Bug 104338</a> - NULL pointer access crash on Sacha Willems' Vulkan raytracing demo after &quot;spirv: Add basic type validation for OpLoad, OpStore, and OpCopyMemory&quot;</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104359">Bug 104359</a> - Mesa freezes in &quot;vtn_cfg_walk_blocks&quot; with Sacha Willems' hdr, parallaxmapping and specializationconstants Vulkan demos</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104381">Bug 104381</a> - swr fails to build since llvm-svn r321257</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104383">Bug 104383</a> - [KBL] Intel GPU hang with firefox</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104411">Bug 104411</a> - [CCS] lemonbar-xft GPU hang</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104424">Bug 104424</a> - DOOM 2016 broken by spirv OpStore validation</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104487">Bug 104487</a> - [KBL] portal2_linux GPU hang</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104490">Bug 104490</a> - [radeonsi/290x] Dota2 fails to start (can't create opengl context)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104492">Bug 104492</a> - Compute Shader: Wrong alignment when assigning struct value to structured SSBO</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104546">Bug 104546</a> - Crash happens when running compute pipeline after calling glxMakeCurrent two times</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104551">Bug 104551</a> - Check if Mako templates for Python are installed</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104625">Bug 104625</a> - semicolon after if</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104636">Bug 104636</a> - [BSW/HD400] Aztec Ruins GL version GPU hangs</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104642">Bug 104642</a> - Android: NULL pointer dereference with i965 mesa-dev, seems build_id_length related</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104654">Bug 104654</a> - r600/sb: Alien Isolation GPU lock</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104668">Bug 104668</a> - dEQP-GLES31.functional.shaders.linkage.uniform.block.differing_precision regression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104677">Bug 104677</a> - radv_generate_graphics_pipeline_key reads input rate from incorrect binding</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104690">Bug 104690</a> - [G33] regression: piglit.spec.!opengl 1_4.draw-batch and gl-1_4-dlist-multidrawarrays</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104711">Bug 104711</a> - [skl CCS] Oxenfree (unity engine game) hangs GPU</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104741">Bug 104741</a> - Graphic corruption for Android apps Telegram and KineMaster</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104742">Bug 104742</a> - [swrast] piglit gl-1.4-dlist-multidrawarrays regression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104746">Bug 104746</a> - [swrast] piglit attribs regression</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104749">Bug 104749</a> - rasterizer/jitter/JitManager.cpp:252:91: error: no matching function for call to ‘llvm::DIBuilder::createBasicType(const char [8], int, llvm::dwarf::TypeKind)’</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104762">Bug 104762</a> - Various segfaults/problems in qt/plasma</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104777">Bug 104777</a> - Attaching multiple shader objects for the same stage to a GLSL program triggers a linker error</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104884">Bug 104884</a> - memory leak with intel i965 mesa when running android container in Ubuntu</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104905">Bug 104905</a> - SpvOpFOrdEqual doesn't return correct results for NaNs</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104915">Bug 104915</a> - Indexed SHADING_LANGUAGE_VERSION query not supported</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104923">Bug 104923</a> - anv: Dota2 rendering corruption</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105013">Bug 105013</a> - [regression] GLX+VA-API+clutter-gst video playback is corrupt with Mesa 17.3 (but is fine with 17.2)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105029">Bug 105029</a> - simdlib_512_avx512.inl:371:57: error: could not convert ‘_mm512_mask_blend_epi32((__mmask16)(ImmT), a, b)’ from ‘__m512i’ {aka ‘__vector(8) long long int’} to ‘SIMDImpl::SIMD512Impl::Float’</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105065">Bug 105065</a> - Qt Programs occasionally fail to render with new Mesa (glGetProgramBinary)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105098">Bug 105098</a> - [RADV] GPU freeze with simple Vulkan App</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105103">Bug 105103</a> - Wayland master causes Mesa to fail to compile</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105120">Bug 105120</a> - meson build broken</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105224">Bug 105224</a> - Webgl Pointclouds flickers</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105255">Bug 105255</a> - Waiting for fences without waitAll is not implemented</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105271">Bug 105271</a> - WebGL2 shader crashes i965_dri.so 17.3.3</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105290">Bug 105290</a> - [BSW/HD400] SynMark OglCSDof GPU hangs when shaders come from cache</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105292">Bug 105292</a> - vkGetQueryPoolResults returns incorrect query status for large query buffers (bisected)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105436">Bug 105436</a> - Blinking textures in UT2004 [bisected]</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105464">Bug 105464</a> - Reading per-patch outputs in Tessellation Control Shader returns undefined values</li>
-
-</ul>
-
-<h2>Changes</h2>
-
-<ul>
-<li>Remove incomplete GLX_MESA_set_3dfx_mode from the Xlib libGL</li>
-</ul>
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.1.html

@@ -1,225 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.1 Release Notes / April 18, 2018</h1>
-
-<p>
-Mesa 18.0.1 is a bug fix release which fixes bugs found since the 18.0.0 release.
-</p>
-<p>
-Mesa 18.0.1 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-0c93ba892c0610f5dd87f2e2673b9445187995c395b3ddb33fd4260bfb291e89  mesa-18.0.1.tar.gz
-b2d2f5b5dbaab13e15cb0dcb5ec81887467f55ebc9625945b303a3647cd87954  mesa-18.0.1.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101408">Bug 101408</a> - [Gen8+] Xonotic fails to render one of the weapons</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102342">Bug 102342</a> - mesa-17.1.7/src/gallium/auxiliary/pipebuffer/pb_cache.c:169]: (style) Suspicious condition</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102542">Bug 102542</a> - mesa-17.2.0/src/gallium/state_trackers/nine/nine_ff.c:1938: bad assignment ?</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105317">Bug 105317</a> - The GPU Vega 56 was hang while try to pass #GraphicsFuzz shader15 test</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105440">Bug 105440</a> - GEN7: rendering issue on citra</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105442">Bug 105442</a> - Hang when running nine ff lighting shader with radeonsi</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105567">Bug 105567</a> - meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105670">Bug 105670</a> - [regression][hang] Trine1EE hangs GPU after loading screen on Mesa3D-17.3 and later</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105704">Bug 105704</a> - compiler assertion hit</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105717">Bug 105717</a> - [bisected] Mesa build tests fails: BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105942">Bug 105942</a> - Graphical artefacts after update to mesa 18.0.0-2</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andres Gomez (2):</p>
-<ul>
-  <li>dri_util: when overriding, always reset the core version</li>
-  <li>mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usage</li>
-</ul>
-
-<p>Axel Davy (5):</p>
-<ul>
-  <li>st/nine: Fix bad tracking of vs textures for NINESBT_ALL</li>
-  <li>st/nine: Fixes warning about implicit conversion</li>
-  <li>st/nine: Fix non inversible matrix check</li>
-  <li>st/nine: Declare lighting consts for ff shaders</li>
-  <li>st/nine: Do not use scratch for face register</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (3):</p>
-<ul>
-  <li>ac/nir: Add workaround for GFX9 buffer views.</li>
-  <li>radv: Don't set instance count using predication.</li>
-  <li>radv: Always reset draw user SGPRs after secondary command buffer.</li>
-</ul>
-
-<p>Caio Marcelo de Oliveira Filho (1):</p>
-<ul>
-  <li>anv/pipeline: fail if TCS/TES compile fail</li>
-</ul>
-
-<p>Daniel Stone (1):</p>
-<ul>
-  <li>st/dri: Initialise modifier to INVALID for DRI2</li>
-</ul>
-
-<p>Derek Foreman (1):</p>
-<ul>
-  <li>egl/wayland: Make swrast display_sync the correct queue</li>
-</ul>
-
-<p>Dylan Baker (4):</p>
-<ul>
-  <li>meson: don't use compiler.has_header</li>
-  <li>autotools: include meson_get_version</li>
-  <li>meson: Set .so version for xa like autotools does</li>
-  <li>meson: fix megadriver symlinking</li>
-</ul>
-
-<p>Emil Velikov (1):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.0</li>
-</ul>
-
-<p>Eric Engestrom (3):</p>
-<ul>
-  <li>meson/configure: detect endian.h instead of trying to guess when it's available</li>
-  <li>docs: fix 18.0 release note version</li>
-  <li>gbm: remove never-implemented function</li>
-</ul>
-
-<p>Henri Verbeet (1):</p>
-<ul>
-  <li>mesa: Inherit texture view multi-sample information from the original texture images.</li>
-</ul>
-
-<p>Iago Toral Quiroga (1):</p>
-<ul>
-  <li>compiler/spirv: set is_shadow for depth comparitor sampling opcodes</li>
-</ul>
-
-<p>Ian Romanick (1):</p>
-<ul>
-  <li>i965/vec4: Fix null destination register in 3-source instructions</li>
-</ul>
-
-<p>Jason Ekstrand (4):</p>
-<ul>
-  <li>nir/vars_to_ssa: Remove copies from the correct set</li>
-  <li>nir/lower_indirect_derefs: Support interp_var_at intrinsics</li>
-  <li>intel/vec4: Set channel_sizes for MOV_INDIRECT sources</li>
-  <li>nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination</li>
-</ul>
-
-<p>Juan A. Suarez Romero (5):</p>
-<ul>
-  <li>cherry-ignore anv: Be more careful about fast-clear colors</li>
-  <li>cherry-ignore: ac/shader: fix vertex input with components.</li>
-  <li>cherry-ignore: radv: handle exporting view index to fragment shader. (v1.1)</li>
-  <li>cherry-ignore: omx: always define ENABLE_ST_OMX_{BELLAGIO,TIZONIA}</li>
-  <li>Update version to 18.0.1</li>
-</ul>
-
-<p>Leo Liu (1):</p>
-<ul>
-  <li>radeon/vce: move feedback command inside of destroy function</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>i965/perf: fix config registration when uploading to kernel</li>
-</ul>
-
-<p>Marc Dietrich (1):</p>
-<ul>
-  <li>meson: fix HAVE_LLVM version define in meson build</li>
-</ul>
-
-<p>Marek Olšák (1):</p>
-<ul>
-  <li>mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API override</li>
-</ul>
-
-<p>Mark Thompson (1):</p>
-<ul>
-  <li>st/va: Enable vaExportSurfaceHandle()</li>
-</ul>
-
-<p>Rob Clark (3):</p>
-<ul>
-  <li>nir: fix per_vertex_output intrinsic</li>
-  <li>freedreno/a5xx: fix page faults on last level</li>
-  <li>freedreno/a5xx: don't align height for PIPE_BUFFER</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>radv: fix picking the method for resolve subpass</li>
-  <li>radv: fix radv_layout_dcc_compressed() when image doesn't have DCC</li>
-</ul>
-
-<p>Sergii Romantsov (1):</p>
-<ul>
-  <li>i965: Extend the negative 32-bit deltas to 64-bits</li>
-</ul>
-
-<p>Timothy Arceri (7):</p>
-<ul>
-  <li>ac: add if/loop build helpers</li>
-  <li>radeonsi: make use of if/loop build helpers in ac</li>
-  <li>ac: make use of if/loop build helpers</li>
-  <li>glsl: fix infinite loop caused by bug in loop unrolling pass</li>
-  <li>nir: fix crash in loop unroll corner case</li>
-  <li>gallium/pipebuffer: fix parenthesis location</li>
-  <li>glsl: always call do_lower_jumps() after loop unrolling</li>
-</ul>
-
-<p>Xiong, James (1):</p>
-<ul>
-  <li>i965: return the fourcc saved in __DRIimage when possible</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.2.html

@@ -1,144 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.2 Release Notes / April 28, 2018</h1>
-
-<p>
-Mesa 18.0.2 is a bug fix release which fixes bugs found since the 18.0.1 release.
-</p>
-<p>
-Mesa 18.0.2 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-SHA256: ffd8dfe3337b474a3baa085f0e7ef1a32c7cdc3bed1ad810b2633919a9324840  mesa-18.0.2.tar.gz
-SHA256: 98fa159768482dc568b9f8bf0f36c7acb823fa47428ffd650b40784f16b9e7b3  mesa-18.0.2.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=95009">Bug 95009</a> - [SNB] amd_shader_trinary_minmax.execution.built-in-functions.gs-mid3-ivec2-ivec2-ivec2 intermittent</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=95012">Bug 95012</a> - [SNB] glsl-1_50.execution.built-in-functions.gs-op tests intermittent</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=98281">Bug 98281</a> - 'message's in ctx-&gt;Debug.LogMessages[] seem to leak.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105320">Bug 105320</a> - Storage texel buffer access produces wrong results (RX Vega)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105775">Bug 105775</a> - SI reaches the maximum IB size in dwords and fail to submit</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105994">Bug 105994</a> - surface state leak when creating and destroying image views with aspectMask depth and stencil</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106074">Bug 106074</a> - radv: si_scissor_from_viewport returns incorrect result when using half-pixel viewport offset</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106126">Bug 106126</a> - eglMakeCurrent does not always ensure dri_drawable-&gt;update_drawable_info has been called for a new EGLSurface if another has been created and destroyed first</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Bas Nieuwenhuizen (2):</p>
-<ul>
-  <li>ac/nir: Make the GFX9 buffer size fix apply to image loads/atomics too.</li>
-  <li>radv: Mark GTT memory as device local for APUs.</li>
-</ul>
-
-<p>Dylan Baker (2):</p>
-<ul>
-  <li>bin/install_megadrivers: fix DESTDIR and -D*-path</li>
-  <li>meson: don't build classic mesa tests without dri_drivers</li>
-</ul>
-
-<p>Ian Romanick (1):</p>
-<ul>
-  <li>intel/compiler: Add scheduler deps for instructions that implicitly read g0</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>i965/fs: Return mlen * 8 for size_read() for INTERPOLATE_AT_*</li>
-</ul>
-
-<p>Johan Klokkhammer Helsing (1):</p>
-<ul>
-  <li>st/dri: Fix dangling pointer to a destroyed dri_drawable</li>
-</ul>
-
-<p>Juan A. Suarez Romero (4):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.1</li>
-  <li>travis: radv needs LLVM 4.0</li>
-  <li>cherry-ignore: add explicit 18.1 only nominations</li>
-  <li>Update version to 18.0.2</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>i965: Fix shadow batches to be the same size as the real BO.</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>anv: fix number of planes for depth &amp; stencil</li>
-</ul>
-
-<p>Lucas Stach (1):</p>
-<ul>
-  <li>etnaviv: fix texture_format_needs_swiz</li>
-</ul>
-
-<p>Marek Olšák (3):</p>
-<ul>
-  <li>radeonsi/gfx9: fix a hang with an empty first IB</li>
-  <li>glsl_to_tgsi: try harder to lower unsupported ir_binop_vector_extract</li>
-  <li>Revert "st/dri: Fix dangling pointer to a destroyed dri_drawable"</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>radv: fix scissor computation when using half-pixel viewport offset</li>
-  <li>radv/winsys: allow to submit up to 4 IBs for chips without chaining</li>
-</ul>
-
-<p>Thomas Hellstrom (1):</p>
-<ul>
-  <li>svga: Fix incorrect advertizing of EGL_KHR_gl_colorspace</li>
-</ul>
-
-<p>Timothy Arceri (1):</p>
-<ul>
-  <li>mesa: free debug messages when destroying the debug state</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.3.html

@@ -1,107 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.3 Release Notes / May 7, 2018</h1>
-
-<p>
-Mesa 18.0.3 is a bug fix release which fixes bugs found since the 18.0.2 release.
-</p>
-<p>
-Mesa 18.0.3 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-58cc5c5b1ab2a44e6e47f18ef6c29836ad06f95450adce635ce3c317507a171b  mesa-18.0.3.tar.gz
-099d9667327a76a61741a533f95067d76ea71a656e66b91507b3c0caf1d49e30  mesa-18.0.3.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105374">Bug 105374</a> - texture3d, a SaschaWillems demo, assert fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106147">Bug 106147</a> - SIGBUS in write_reloc() when Sacha Willems' &quot;texture3d&quot; Vulkan demo starts</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andres Rodriguez (1):</p>
-<ul>
-  <li>radv/winsys: fix leaking resources from bo's imported by fd</li>
-</ul>
-
-<p>Boyuan Zhang (1):</p>
-<ul>
-  <li>radeon/vcn: fix mpeg4 msg buffer settings</li>
-</ul>
-
-<p>Eric Anholt (1):</p>
-<ul>
-  <li>gallium/util: Fix incorrect refcounting of separate stencil.</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>anv/allocator: Don't shrink either end of the block pool</li>
-</ul>
-
-<p>Juan A. Suarez Romero (3):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.2</li>
-  <li>cherry-ignore: add explicit 18.1 only nominations</li>
-  <li>Update version to 18.0.3</li>
-</ul>
-
-<p>Leo Liu (1):</p>
-<ul>
-  <li>st/omx/enc: fix blit setup for YUV LoadImage</li>
-</ul>
-
-<p>Marek Olšák (2):</p>
-<ul>
-  <li>util/u_queue: fix a deadlock in util_queue_finish</li>
-  <li>radeonsi/gfx9: workaround for INTERP with indirect indexing</li>
-</ul>
-
-<p>Nanley Chery (1):</p>
-<ul>
-  <li>i965/tex_image: Avoid the ASTC LDR workaround on gen9lp</li>
-</ul>
-
-<p>Samuel Pitoiset (1):</p>
-<ul>
-  <li>radv: compute the number of subpass attachments correctly</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.4.html

@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.4 Release Notes / May 17, 2018</h1>
-
-<p>
-Mesa 18.0.4 is a bug fix release which fixes bugs found since the 18.0.3 release.
-</p>
-<p>
-Mesa 18.0.4 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-d1dc3469faccdd73439479426952d71a9e8f684e8d03b6687063c12b13430801  mesa-18.0.4.tar.gz
-1f3bcfe7cef0a5c20dae2b41df5d7e0a985e06be0183fa4d43b6068fcba2920f  mesa-18.0.4.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91808">Bug 91808</a> - trine1 misrender r600g</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100430">Bug 100430</a> - [radv] graphical glitches on dolphin emulator</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106243">Bug 106243</a> - [kbl] GPU HANG: 9:0:0x85dffffb, in Cinnamon</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106480">Bug 106480</a> - A2B10G10R10_SNORM vertex attribute doesn't work.</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Bas Nieuwenhuizen (3):</p>
-<ul>
-  <li>radv: Translate logic ops.</li>
-  <li>radv: Fix up 2_10_10_10 alpha sign.</li>
-  <li>radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.</li>
-</ul>
-
-<p>Dave Airlie (3):</p>
-<ul>
-  <li>r600: fix constant buffer bounds.</li>
-  <li>radv: resolve all layers in compute resolve path.</li>
-  <li>radv: use compute path for multi-layer images.</li>
-</ul>
-
-<p>Deepak Rawat (1):</p>
-<ul>
-  <li>egl/x11: Send invalidate to driver on copy_region path in swap_buffer</li>
-</ul>
-
-<p>Ian Romanick (1):</p>
-<ul>
-  <li>mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)</li>
-</ul>
-
-<p>Jan Vesely (8):</p>
-<ul>
-  <li>clover: Add explicit virtual destructor to argument class</li>
-  <li>eg/compute: Drop reference on code_bo in destructor.</li>
-  <li>r600: Cleanup constant buffers on context destruction</li>
-  <li>eg/compute: Drop reference to kernel_param bo in destructor</li>
-  <li>pipe-loader: Free driver_name in error path</li>
-  <li>gallium/auxiliary: Add helper function to count the number of entries in hash table</li>
-  <li>winsys/radeon: Destroy fd_hash table when the last winsys is removed.</li>
-  <li>winsys/amdgpu: Destroy dev_hash table when the last winsys is removed.</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL</li>
-</ul>
-
-<p>Jose Maria Casanova Crespo (2):</p>
-<ul>
-  <li>intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate</li>
-  <li>intel/compiler: fix brw_imm_w for negative 16-bit integers</li>
-</ul>
-
-<p>Juan A. Suarez Romero (7):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.3</li>
-  <li>cherry-ignore: add explicit 18.1 only nominations</li>
-  <li>cherry-ignore: glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug</li>
-  <li>cherry-ignore: mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs</li>
-  <li>cherry-ignore: mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT</li>
-  <li>cherry-ignore: radv/resolve: do fmask decompress on all layers.</li>
-  <li>Update version to 18.0.4</li>
-</ul>
-
-<p>Kai Wasserbäch (1):</p>
-<ul>
-  <li>opencl: autotools: Fix linking order for OpenCL target</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>i965: Don't leak blorp on Gen4-5.</li>
-</ul>
-
-<p>Lionel Landwerlin (2):</p>
-<ul>
-  <li>i965: require pixel scoreboard stall prior to ISP disable</li>
-  <li>anv: emit pixel scoreboard stall before ISP disable</li>
-</ul>
-
-<p>Matthew Nicholls (1):</p>
-<ul>
-  <li>radv: fix multisample image copies</li>
-</ul>
-
-<p>Neil Roberts (1):</p>
-<ul>
-  <li>spirv: Apply OriginUpperLeft to FragCoord</li>
-</ul>
-
-<p>Rhys Perry (1):</p>
-<ul>
-  <li>mesa: fix error handling in get_framebuffer_parameteriv</li>
-</ul>
-
-<p>Ross Burton (1):</p>
-<ul>
-  <li>src/intel/Makefile.vulkan.am: add missing MKDIR_GEN</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.5.html

@@ -1,161 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.5 Release Notes / June 3, 2018</h1>
-
-<p>
-Mesa 18.0.5 is a bug fix release which fixes bugs found since the 18.0.4 release.
-</p>
-<p>
-Mesa 18.0.5 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-TBD
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=78097">Bug 78097</a> - glUniform1ui and friends not supported by display lists</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102390">Bug 102390</a> - centroid interpolation causes broken attribute values</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105351">Bug 105351</a> - [Gen6+] piglit's arb_shader_image_load_store-host-mem-barrier fails with a glGetTexSubImage fallback path</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106090">Bug 106090</a> - Compiling compute shader crashes RADV</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106315">Bug 106315</a> - The witness + dxvk suffers flickering garbage</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106465">Bug 106465</a> - No test for Image Load/Store on format-incompatible texture buffer</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106479">Bug 106479</a> - NDEBUG not defined for libamdgpu_addrlib</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106481">Bug 106481</a> - No test for Image Load/Store on texture buffer sized greater than MAX_TEXTURE_BUFFER_SIZE_ARB</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106504">Bug 106504</a> - vulkan SPIR-V parsing failed at ../src/compiler/spirv/vtn_cfg.c:381</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106587">Bug 106587</a> - Dota2 is very dark when using vulkan render on a Intel &lt;&lt; AMD prime setup</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106629">Bug 106629</a> - [SNB,IVB,HSW,BDW] dEQP-EGL.functional.image.create.gles2_cubemap_negative_z_rgb_read_pixels</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Anuj Phogat (1):</p>
-<ul>
-  <li>i965/glk: Add l3 banks count for 2x6 configuration</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (2):</p>
-<ul>
-  <li>amd/addrlib: Use defines in autotools build.</li>
-  <li>radv: Fix SRGB compute copies.</li>
-</ul>
-
-<p>Dave Airlie (1):</p>
-<ul>
-  <li>tgsi/scan: add hw atomic to the list of memory accessing files</li>
-</ul>
-
-<p>Francisco Jerez (4):</p>
-<ul>
-  <li>Revert "mesa: simplify _mesa_is_image_unit_valid for buffers"</li>
-  <li>i965: Move buffer texture size calculation into a common helper function.</li>
-  <li>i965: Handle non-zero texture buffer offsets in buffer object range calculation.</li>
-  <li>i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.</li>
-</ul>
-
-<p>Jan Vesely (1):</p>
-<ul>
-  <li>eg/compute: Use reference counting to handle compute memory pool.</li>
-</ul>
-
-<p>Jason Ekstrand (2):</p>
-<ul>
-  <li>intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0</li>
-  <li>intel/blorp: Support blits and clears on surfaces with offsets</li>
-</ul>
-
-<p>Jose Dapena Paz (1):</p>
-<ul>
-  <li>mesa: do not leak ctx-&gt;Shader.ReferencedProgram references</li>
-</ul>
-
-<p>Juan A. Suarez Romero (8):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.4</li>
-  <li>cherry-ignore: i965/miptree: Fix handling of uninitialized MCS buffers</li>
-  <li>cherry-ignore: add explicit 18.1 only nominations</li>
-  <li>cherry-ignore: mesa/st: handle vert_attrib_mask in nir case too</li>
-  <li>cherry-ignore: Tegra is not supported</li>
-  <li>cherry-ignore: st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)</li>
-  <li>cherry-ignore: nv30: ensure that displayable formats are marked accordingly</li>
-  <li>Update version to 18.0.5</li>
-</ul>
-
-<p>Marek Olšák (3):</p>
-<ul>
-  <li>st/mesa: simplify lastLevel determination in st_finalize_texture</li>
-  <li>radeonsi: fix incorrect parentheses around VS-PS varying elimination</li>
-  <li>mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)</li>
-</ul>
-
-<p>Michel Dänzer (1):</p>
-<ul>
-  <li>dri3: Stricter SBC wraparound handling</li>
-</ul>
-
-<p>Nanley Chery (1):</p>
-<ul>
-  <li>i965/miptree: Zero-initialize CCS_D buffers</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>spirv: fix visiting inner loops with same break/continue block</li>
-  <li>radv: fix centroid interpolation</li>
-</ul>
-
-<p>Stuart Young (1):</p>
-<ul>
-  <li>etnaviv: Fix missing rnndb file in tarballs</li>
-</ul>
-
-<p>Timothy Arceri (1):</p>
-<ul>
-  <li>mesa: add glUniform*ui{v} support to display lists</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/specs/MESA_agp_offset.spec

@@ -13,7 +13,8 @@ Contact
 
 Status
 
-    Obsolete. Effectively superseded by ARB_vertex_buffer_object.
+    Shipping (Mesa 4.0.4 and later.  Only implemented in particular
+    XFree86/DRI drivers.)
 
 Version
 

docs/specs/MESA_set_3dfx_mode.spec

@@ -12,7 +12,7 @@ Contact
 
 Status
 
-    Obsolete.
+    Shipping since Mesa 2.6 in February, 1998.
 
 Version
 

docs/specs/OLD/MESA_program_debug.spec

@@ -12,7 +12,7 @@ Contact
 
 Status
 
-    Obsolete.
+    XXX - Not complete yet!!!
 
 Version
 

docs/specs/enums.txt

@@ -63,9 +63,6 @@ GL_MESAX_texture_stack:
 	GL_TEXTURE_1D_STACK_BINDING_MESAX    0x875D
 	GL_TEXTURE_2D_STACK_BINDING_MESAX    0x875E
 
-GL_MESA_program_binary_formats:
-        GL_PROGRAM_BINARY_FORMAT_MESA           0x875F
-
 GL_MESA_tile_raster_order
 	GL_TILE_RASTER_ORDER_FIXED_MESA		0x8BB8
 	GL_TILE_RASTER_ORDER_INCREASING_X_MESA	0x8BB9

include/GL/glext.h

@@ -9212,11 +9212,6 @@ GLAPI void APIENTRY glGetPerfQueryInfoINTEL (GLuint queryId, GLuint queryNameLen
 #define GL_PACK_INVERT_MESA               0x8758
 #endif /* GL_MESA_pack_invert */
 
-#ifndef GL_MESA_program_binary_formats
-#define GL_MESA_program_binary_formats 1
-#define GL_PROGRAM_BINARY_FORMAT_MESA     0x875F
-#endif /* GL_MESA_program_binary_formats */
-
 #ifndef GL_MESA_resize_buffers
 #define GL_MESA_resize_buffers 1
 typedef void (APIENTRYP PFNGLRESIZEBUFFERSMESAPROC) (void);

include/GL/internal/dri_interface.h

@@ -1106,16 +1106,6 @@ struct __DRIdri2LoaderExtensionRec {
 #define __DRI_CTX_PRIORITY_MEDIUM		1
 #define __DRI_CTX_PRIORITY_HIGH			2
 
-/**
- * \name Context release behaviors.
- */
-/*@{*/
-#define __DRI_CTX_ATTRIB_RELEASE_BEHAVIOR	5
-
-#define __DRI_CTX_RELEASE_BEHAVIOR_NONE         0
-#define __DRI_CTX_RELEASE_BEHAVIOR_FLUSH        1
-/*@}*/
-
 /**
  * \name Reasons that __DRIdri2Extension::createContextAttribs might fail
  */
@@ -1226,7 +1216,6 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FORMAT_ARGB1555     0x100c
 #define __DRI_IMAGE_FORMAT_R16          0x100d
 #define __DRI_IMAGE_FORMAT_GR1616       0x100e
-#define __DRI_IMAGE_FORMAT_YUYV         0x100f
 
 #define __DRI_IMAGE_USE_SHARE		0x0001
 #define __DRI_IMAGE_USE_SCANOUT		0x0002
@@ -1262,15 +1251,7 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FOURCC_XRGB8888	0x34325258
 #define __DRI_IMAGE_FOURCC_ABGR8888	0x34324241
 #define __DRI_IMAGE_FOURCC_XBGR8888	0x34324258
-#define __DRI_IMAGE_FOURCC_SARGB8888	0x83324258
-#define __DRI_IMAGE_FOURCC_ARGB2101010	0x30335241
-#define __DRI_IMAGE_FOURCC_XRGB2101010	0x30335258
-#define __DRI_IMAGE_FOURCC_ABGR2101010	0x30334241
-#define __DRI_IMAGE_FOURCC_XBGR2101010	0x30334258
-#define __DRI_IMAGE_FOURCC_RGBA1010102	0x30334152
-#define __DRI_IMAGE_FOURCC_RGBX1010102	0x30335852
-#define __DRI_IMAGE_FOURCC_BGRA1010102	0x30334142
-#define __DRI_IMAGE_FOURCC_BGRX1010102	0x30335842
+#define __DRI_IMAGE_FOURCC_SARGB8888    0x83324258
 #define __DRI_IMAGE_FOURCC_YUV410	0x39565559
 #define __DRI_IMAGE_FOURCC_YUV411	0x31315559
 #define __DRI_IMAGE_FOURCC_YUV420	0x32315559
@@ -1734,21 +1715,6 @@ typedef struct __DRInoErrorExtensionRec {
    __DRIextension base;
 } __DRInoErrorExtension;
 
-/*
- * Flush control driver extension.
- *
- * Existence of this extension means the driver can accept the
- * \c __DRI_CTX_ATTRIB_RELEASE_BEHAVIOR attribute in
- * \c __DRIdri2ExtensionRec::createContextAttribs.
- */
-#define __DRI2_FLUSH_CONTROL "DRI_FlushControl"
-#define __DRI2_FLUSH_CONTROL_VERSION 1
-
-typedef struct __DRI2flushControlExtensionRec __DRI2flushControlExtension;
-struct __DRI2flushControlExtensionRec {
-   __DRIextension base;
-};
-
 /**
  * DRI config options extension.
  *

include/GLES2/gl2ext.h

@@ -2334,11 +2334,6 @@ GL_APICALL void GL_APIENTRY glGetPerfQueryInfoINTEL (GLuint queryId, GLuint quer
 #endif
 #endif /* GL_INTEL_performance_query */
 
-#ifndef GL_MESA_program_binary_formats
-#define GL_MESA_program_binary_formats 1
-#define GL_PROGRAM_BINARY_FORMAT_MESA     0x875F
-#endif /* GL_MESA_program_binary_formats */
-
 #ifndef GL_MESA_shader_integer_functions
 #define GL_MESA_shader_integer_functions 1
 #endif /* GL_MESA_shader_integer_functions */

include/c11/threads.h

@@ -30,6 +30,9 @@
 #define EMULATED_THREADS_H_INCLUDED_
 
 #include <time.h>
+#ifdef _MSC_VER
+#include <thr/xtimec.h>  // for xtime
+#endif
 
 #ifndef TIME_UTC
 #define TIME_UTC 1
@@ -41,6 +44,14 @@
 typedef void (*tss_dtor_t)(void*);
 typedef int (*thrd_start_t)(void*);
 
+#ifndef _MSC_VER
+struct xtime {
+    time_t sec;
+    long nsec;
+};
+typedef struct xtime xtime;
+#endif
+
 
 /*-------------------- enumeration constants --------------------*/
 enum {

include/c11/threads_posix.h

@@ -132,15 +132,19 @@ cnd_signal(cnd_t *cond)
 
 // 7.25.3.5
 static inline int
-cnd_timedwait(cnd_t *cond, mtx_t *mtx, const struct timespec *abs_time)
+cnd_timedwait(cnd_t *cond, mtx_t *mtx, const xtime *xt)
 {
+    struct timespec abs_time;
     int rt;
 
     assert(mtx != NULL);
     assert(cond != NULL);
-    assert(abs_time != NULL);
+    assert(xt != NULL);
 
-    rt = pthread_cond_timedwait(cond, mtx, abs_time);
+    abs_time.tv_sec = xt->sec;
+    abs_time.tv_nsec = xt->nsec;
+
+    rt = pthread_cond_timedwait(cond, mtx, &abs_time);
     if (rt == ETIMEDOUT)
         return thrd_busy;
     return (rt == 0) ? thrd_success : thrd_error;
@@ -231,21 +235,24 @@ thrd_yield(void);
 
 // 7.25.4.4
 static inline int
-mtx_timedlock(mtx_t *mtx, const struct timespec *ts)
+mtx_timedlock(mtx_t *mtx, const xtime *xt)
 {
     assert(mtx != NULL);
-    assert(ts != NULL);
+    assert(xt != NULL);
 
     {
 #ifdef EMULATED_THREADS_USE_NATIVE_TIMEDLOCK
+    struct timespec ts;
     int rt;
-    rt = pthread_mutex_timedlock(mtx, ts);
+    ts.tv_sec = xt->sec;
+    ts.tv_nsec = xt->nsec;
+    rt = pthread_mutex_timedlock(mtx, &ts);
     if (rt == 0)
         return thrd_success;
     return (rt == ETIMEDOUT) ? thrd_busy : thrd_error;
 #else
     time_t expire = time(NULL);
-    expire += ts->tv_sec;
+    expire += xt->sec;
     while (mtx_trylock(mtx) != thrd_success) {
         time_t now = time(NULL);
         if (expire < now)
@@ -335,10 +342,13 @@ thrd_join(thrd_t thr, int *res)
 
 // 7.25.5.7
 static inline void
-thrd_sleep(const struct timespec *time_point, struct timespec *remaining)
+thrd_sleep(const xtime *xt)
 {
-    assert(time_point != NULL);
-    nanosleep(time_point, remaining);
+    struct timespec req;
+    assert(xt);
+    req.tv_sec = xt->sec;
+    req.tv_nsec = xt->nsec;
+    nanosleep(&req, NULL);
 }
 
 // 7.25.5.8
@@ -382,15 +392,14 @@ tss_set(tss_t key, void *val)
 
 /*-------------------- 7.25.7 Time functions --------------------*/
 // 7.25.6.1
-#ifndef HAVE_TIMESPEC_GET
 static inline int
-timespec_get(struct timespec *ts, int base)
+xtime_get(xtime *xt, int base)
 {
-    if (!ts) return 0;
+    if (!xt) return 0;
     if (base == TIME_UTC) {
-        clock_gettime(CLOCK_REALTIME, ts);
+        xt->sec = time(NULL);
+        xt->nsec = 0;
         return base;
     }
     return 0;
 }
-#endif

include/c11/threads_win32.h

@@ -75,20 +75,6 @@ Configuration macro:
 #error EMULATED_THREADS_USE_NATIVE_CV requires _WIN32_WINNT>=0x0600
 #endif
 
-/* Visual Studio 2015 and later */
-#if _MSC_VER >= 1900
-#define HAVE_TIMESPEC
-#define HAVE_TIMESPEC_GET
-#elif defined(__MINGW32__)
-#define HAVE_TIMESPEC
-#endif
-
-#ifndef HAVE_TIMESPEC
-struct timespec {
-    time_t tv_sec;
-    long tv_nsec;
-};
-#endif
 
 /*---------------------------- macros ----------------------------*/
 #ifdef EMULATED_THREADS_USE_NATIVE_CALL_ONCE
@@ -160,9 +146,9 @@ static unsigned __stdcall impl_thrd_routine(void *p)
     return (unsigned)code;
 }
 
-static DWORD impl_timespec2msec(const struct timespec *ts)
+static DWORD impl_xtime2msec(const xtime *xt)
 {
-    return (DWORD)((ts->tv_sec * 1000U) + (ts->tv_nsec / 1000000L));
+    return (DWORD)((xt->sec * 1000U) + (xt->nsec / 1000000L));
 }
 
 #ifdef EMULATED_THREADS_USE_NATIVE_CALL_ONCE
@@ -220,7 +206,7 @@ static void impl_cond_do_signal(cnd_t *cond, int broadcast)
         ReleaseSemaphore(cond->sem_queue, nsignal, NULL);
 }
 
-static int impl_cond_do_wait(cnd_t *cond, mtx_t *mtx, const struct timespec *ts)
+static int impl_cond_do_wait(cnd_t *cond, mtx_t *mtx, const xtime *xt)
 {
     int nleft = 0;
     int ngone = 0;
@@ -233,7 +219,7 @@ static int impl_cond_do_wait(cnd_t *cond, mtx_t *mtx, const struct timespec *ts)
 
     mtx_unlock(mtx);
 
-    w = WaitForSingleObject(cond->sem_queue, ts ? impl_timespec2msec(ts) : INFINITE);
+    w = WaitForSingleObject(cond->sem_queue, xt ? impl_xtime2msec(xt) : INFINITE);
     timeout = (w == WAIT_TIMEOUT);
  
     EnterCriticalSection(&cond->monitor);
@@ -392,15 +378,15 @@ cnd_signal(cnd_t *cond)
 
 // 7.25.3.5
 static inline int
-cnd_timedwait(cnd_t *cond, mtx_t *mtx, const struct timespec *abs_time)
+cnd_timedwait(cnd_t *cond, mtx_t *mtx, const xtime *xt)
 {
-    if (!cond || !mtx || !abs_time) return thrd_error;
+    if (!cond || !mtx || !xt) return thrd_error;
 #ifdef EMULATED_THREADS_USE_NATIVE_CV
-    if (SleepConditionVariableCS(&cond->condvar, mtx, impl_timespec2msec(abs_time)))
+    if (SleepConditionVariableCS(&cond->condvar, mtx, impl_xtime2msec(xt)))
         return thrd_success;
     return (GetLastError() == ERROR_TIMEOUT) ? thrd_busy : thrd_error;
 #else
-    return impl_cond_do_wait(cond, mtx, abs_time);
+    return impl_cond_do_wait(cond, mtx, xt);
 #endif
 }
 
@@ -452,12 +438,12 @@ mtx_lock(mtx_t *mtx)
 
 // 7.25.4.4
 static inline int
-mtx_timedlock(mtx_t *mtx, const struct timespec *ts)
+mtx_timedlock(mtx_t *mtx, const xtime *xt)
 {
     time_t expire, now;
-    if (!mtx || !ts) return thrd_error;
+    if (!mtx || !xt) return thrd_error;
     expire = time(NULL);
-    expire += ts->tv_sec;
+    expire += xt->sec;
     while (mtx_trylock(mtx) != thrd_success) {
         now = time(NULL);
         if (expire < now)
@@ -593,11 +579,10 @@ thrd_join(thrd_t thr, int *res)
 
 // 7.25.5.7
 static inline void
-thrd_sleep(const struct timespec *time_point, struct timespec *remaining)
+thrd_sleep(const xtime *xt)
 {
-    assert(time_point);
-    assert(!remaining); /* not implemented */
-    Sleep(impl_timespec2msec(time_point));
+    assert(xt);
+    Sleep(impl_xtime2msec(xt));
 }
 
 // 7.25.5.8
@@ -648,16 +633,14 @@ tss_set(tss_t key, void *val)
 
 /*-------------------- 7.25.7 Time functions --------------------*/
 // 7.25.6.1
-#ifndef HAVE_TIMESPEC_GET
 static inline int
-timespec_get(struct timespec *ts, int base)
+xtime_get(xtime *xt, int base)
 {
-    if (!ts) return 0;
+    if (!xt) return 0;
     if (base == TIME_UTC) {
-        ts->tv_sec = time(NULL);
-        ts->tv_nsec = 0;
+        xt->sec = time(NULL);
+        xt->nsec = 0;
         return base;
     }
     return 0;
 }
-#endif

include/c99_compat.h

@@ -164,7 +164,6 @@ test_c99_compat_h(const void * restrict a,
 #    define HAVE_FUNC_ATTRIBUTE_FORMAT 1
 #    define HAVE_FUNC_ATTRIBUTE_PACKED 1
 #    define HAVE_FUNC_ATTRIBUTE_ALIAS 1
-#    define HAVE_FUNC_ATTRIBUTE_NORETURN 1
 
 #    if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)
        /* https://gcc.gnu.org/onlinedocs/gcc-4.3.6/gcc/Other-Builtins.html */

include/drm-uapi/README

@@ -13,9 +13,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
 
 The last update was done at the following kernel commit :
 
-commit ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59
-Merge: 2c1c55cb75a9 010d118c2061
+commit 7846b12fe0b5feab5446d892f41b5140c1419109
+Merge: 7ebdb0d d78acfe
 Author: Dave Airlie <airlied@redhat.com>
-Date:   Mon Dec 4 09:40:35 2017 +1000
+Date:   Tue Aug 29 10:38:14 2017 +1000
 
-    Merge tag 'drm-intel-next-2017-11-17-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
+    Merge branch 'drm-vmwgfx-next' of git://people.freedesktop.org/~syeh/repos_linux into drm-next

include/drm-uapi/drm.h

@@ -731,28 +731,6 @@ struct drm_syncobj_array {
 	__u32 pad;
 };
 
-/* Query current scanout sequence number */
-struct drm_crtc_get_sequence {
-	__u32 crtc_id;		/* requested crtc_id */
-	__u32 active;		/* return: crtc output is active */
-	__u64 sequence;		/* return: most recent vblank sequence */
-	__s64 sequence_ns;	/* return: most recent time of first pixel out */
-};
-
-/* Queue event to be delivered at specified sequence. Time stamp marks
- * when the first pixel of the refresh cycle leaves the display engine
- * for the display
- */
-#define DRM_CRTC_SEQUENCE_RELATIVE		0x00000001	/* sequence is relative to current */
-#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS		0x00000002	/* Use next sequence if we've missed */
-
-struct drm_crtc_queue_sequence {
-	__u32 crtc_id;
-	__u32 flags;
-	__u64 sequence;		/* on input, target sequence. on output, actual sequence */
-	__u64 user_data;	/* user data passed to event */
-};
-
 #if defined(__cplusplus)
 }
 #endif
@@ -835,9 +813,6 @@ extern "C" {
 
 #define DRM_IOCTL_WAIT_VBLANK		DRM_IOWR(0x3a, union drm_wait_vblank)
 
-#define DRM_IOCTL_CRTC_GET_SEQUENCE	DRM_IOWR(0x3b, struct drm_crtc_get_sequence)
-#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE	DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)
-
 #define DRM_IOCTL_UPDATE_DRAW		DRM_IOW(0x3f, struct drm_update_draw)
 
 #define DRM_IOCTL_MODE_GETRESOURCES	DRM_IOWR(0xA0, struct drm_mode_card_res)
@@ -882,11 +857,6 @@ extern "C" {
 #define DRM_IOCTL_SYNCOBJ_RESET		DRM_IOWR(0xC4, struct drm_syncobj_array)
 #define DRM_IOCTL_SYNCOBJ_SIGNAL	DRM_IOWR(0xC5, struct drm_syncobj_array)
 
-#define DRM_IOCTL_MODE_CREATE_LEASE	DRM_IOWR(0xC6, struct drm_mode_create_lease)
-#define DRM_IOCTL_MODE_LIST_LESSEES	DRM_IOWR(0xC7, struct drm_mode_list_lessees)
-#define DRM_IOCTL_MODE_GET_LEASE	DRM_IOWR(0xC8, struct drm_mode_get_lease)
-#define DRM_IOCTL_MODE_REVOKE_LEASE	DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
-
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.
@@ -917,7 +887,6 @@ struct drm_event {
 
 #define DRM_EVENT_VBLANK 0x01
 #define DRM_EVENT_FLIP_COMPLETE 0x02
-#define DRM_EVENT_CRTC_SEQUENCE	0x03
 
 struct drm_event_vblank {
 	struct drm_event base;
@@ -928,16 +897,6 @@ struct drm_event_vblank {
 	__u32 crtc_id; /* 0 on older kernels that do not support this */
 };
 
-/* Event delivered at sequence. Time stamp marks when the first pixel
- * of the refresh cycle leaves the display engine for the display
- */
-struct drm_event_crtc_sequence {
-	struct drm_event	base;
-	__u64			user_data;
-	__s64			time_ns;
-	__u64			sequence;
-};
-
 /* typedef area */
 typedef struct drm_clip_rect drm_clip_rect_t;
 typedef struct drm_drawable_info drm_drawable_info_t;

include/drm-uapi/drm_mode.h

@@ -749,9 +749,9 @@ struct drm_format_modifier {
 	 * If the number formats grew to 128, and formats 98-102 are
 	 * supported with the modifier:
 	 *
-	 * 0x0000007c00000000 0000000000000000
+	 * 0x0000003c00000000 0000000000000000
 	 *		  ^
-	 *		  |__offset = 64, formats = 0x7c00000000
+	 *		  |__offset = 64, formats = 0x3c00000000
 	 *
 	 */
 	__u64 formats;
@@ -782,72 +782,6 @@ struct drm_mode_destroy_blob {
 	__u32 blob_id;
 };
 
-/**
- * Lease mode resources, creating another drm_master.
- */
-struct drm_mode_create_lease {
-	/** Pointer to array of object ids (__u32) */
-	__u64 object_ids;
-	/** Number of object ids */
-	__u32 object_count;
-	/** flags for new FD (O_CLOEXEC, etc) */
-	__u32 flags;
-
-	/** Return: unique identifier for lessee. */
-	__u32 lessee_id;
-	/** Return: file descriptor to new drm_master file */
-	__u32 fd;
-};
-
-/**
- * List lesses from a drm_master
- */
-struct drm_mode_list_lessees {
-	/** Number of lessees.
-	 * On input, provides length of the array.
-	 * On output, provides total number. No
-	 * more than the input number will be written
-	 * back, so two calls can be used to get
-	 * the size and then the data.
-	 */
-	__u32 count_lessees;
-	__u32 pad;
-
-	/** Pointer to lessees.
-	 * pointer to __u64 array of lessee ids
-	 */
-	__u64 lessees_ptr;
-};
-
-/**
- * Get leased objects
- */
-struct drm_mode_get_lease {
-	/** Number of leased objects.
-	 * On input, provides length of the array.
-	 * On output, provides total number. No
-	 * more than the input number will be written
-	 * back, so two calls can be used to get
-	 * the size and then the data.
-	 */
-	__u32 count_objects;
-	__u32 pad;
-
-	/** Pointer to objects.
-	 * pointer to __u32 array of object ids
-	 */
-	__u64 objects_ptr;
-};
-
-/**
- * Revoke lease
- */
-struct drm_mode_revoke_lease {
-	/** Unique ID of lessee
-	 */
-	__u32 lessee_id;
-};
-
 #if defined(__cplusplus)
 }
 #endif

include/drm-uapi/i915_drm.h

@@ -86,22 +86,6 @@ enum i915_mocs_table_index {
 	I915_MOCS_CACHED,
 };
 
-/*
- * Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
- */
-enum drm_i915_gem_engine_class {
-	I915_ENGINE_CLASS_RENDER	= 0,
-	I915_ENGINE_CLASS_COPY		= 1,
-	I915_ENGINE_CLASS_VIDEO		= 2,
-	I915_ENGINE_CLASS_VIDEO_ENHANCE	= 3,
-
-	I915_ENGINE_CLASS_INVALID	= -1
-};
-
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
@@ -466,27 +450,6 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY  49
 
-/*
- * Query whether every context (both per-file default and user created) is
- * isolated (insofar as HW supports). If this parameter is not true, then
- * freshly created contexts may inherit values from an existing context,
- * rather than default HW values. If true, it also ensures (insofar as HW
- * supports) that all state set by this context will not leak to any other
- * context.
- *
- * As not every engine across every gen support contexts, the returned
- * value reports the support of context isolation for individual engines by
- * returning a bitmask of each engine class set to true if that class supports
- * isolation.
- */
-#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
-
-/* Frequency of the command streamer timestamps given by the *_TIMESTAMP
- * registers. This used to be fixed per platform but from CNL onwards, this
- * might vary depending on the parts.
- */
-#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
-
 typedef struct drm_i915_getparam {
 	__s32 param;
 	/*
@@ -876,7 +839,6 @@ struct drm_i915_gem_exec_fence {
 
 #define I915_EXEC_FENCE_WAIT            (1<<0)
 #define I915_EXEC_FENCE_SIGNAL          (1<<1)
-#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
 	__u32 flags;
 };
 

include/drm-uapi/vc4_drm.h

@@ -41,7 +41,6 @@ extern "C" {
 #define DRM_VC4_SET_TILING                        0x08
 #define DRM_VC4_GET_TILING                        0x09
 #define DRM_VC4_LABEL_BO                          0x0a
-#define DRM_VC4_GEM_MADVISE                       0x0b
 
 #define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
 #define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
@@ -54,7 +53,6 @@ extern "C" {
 #define DRM_IOCTL_VC4_SET_TILING          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
 #define DRM_IOCTL_VC4_GET_TILING          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
 #define DRM_IOCTL_VC4_LABEL_BO            DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
-#define DRM_IOCTL_VC4_GEM_MADVISE         DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
 
 struct drm_vc4_submit_rcl_surface {
 	__u32 hindex; /* Handle index, or ~0 if not present. */
@@ -307,7 +305,6 @@ struct drm_vc4_get_hang_state {
 #define DRM_VC4_PARAM_SUPPORTS_ETC1		4
 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS	5
 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER	6
-#define DRM_VC4_PARAM_SUPPORTS_MADVISE		7
 
 struct drm_vc4_get_param {
 	__u32 param;
@@ -336,22 +333,6 @@ struct drm_vc4_label_bo {
 	__u64 name;
 };
 
-/*
- * States prefixed with '__' are internal states and cannot be passed to the
- * DRM_IOCTL_VC4_GEM_MADVISE ioctl.
- */
-#define VC4_MADV_WILLNEED			0
-#define VC4_MADV_DONTNEED			1
-#define __VC4_MADV_PURGED			2
-#define __VC4_MADV_NOTSUPP			3
-
-struct drm_vc4_gem_madvise {
-	__u32 handle;
-	__u32 madv;
-	__u32 retained;
-	__u32 pad;
-};
-
 #if defined(__cplusplus)
 }
 #endif

include/meson.build

@@ -20,8 +20,6 @@
 
 inc_drm_uapi = include_directories('drm-uapi')
 inc_vulkan = include_directories('vulkan')
-inc_d3d9 = include_directories('D3D9')
-inc_gl_internal = include_directories('GL/internal')
 
 if with_gles1
   install_headers(
@@ -36,13 +34,13 @@ if with_gles2
     subdir : 'GLES2',
   )
   install_headers(
-    'GLES3/gl3.h', 'GLES3/gl31.h', 'GLES3/gl32.h', 'GLES3/gl3ext.h',
+    'GLES3/gl3.h', 'GLES3/gl32.h', 'GLES3/gl32.h', 'GLES3/gl3ext.h',
     'GLES3/gl3platform.h',
     subdir : 'GLES3',
   )
 endif
 
-if with_gles1 or with_gles2 or with_egl
+if with_gles1 or with_gles2 # or with_egl
   install_headers('KHR/khrplatform.h', subdir : 'KHR')
 endif
 
@@ -54,10 +52,10 @@ if with_opengl
 endif
 
 if with_glx != 'disabled'
-  install_headers('GL/glx.h', 'GL/glxext.h', 'GL/glx_mangle.h', subdir : 'GL')
+  install_headers('GL/glx.h', 'GL/glext.h', 'GL/glx_mangle.h', subdir : 'GL')
 endif
 
-if with_osmesa != 'none'
+if with_osmesa
   install_headers('GL/osmesa.h', subdir : 'GL')
 endif
 
@@ -68,37 +66,3 @@ if with_egl
     subdir : 'EGL',
   )
 endif
-
-if with_dri
-  install_headers('GL/internal/dri_interface.h', subdir : 'GL/internal')
-endif
-
-if with_gallium_st_nine
-  install_headers(
-    'd3dadapter/d3dadapter9.h', 'd3dadapter/drm.h', 'd3dadapter/present.h',
-    subdir : 'd3dadapter',
-  )
-endif
-
-# Only install the headers if we are building a stand alone implementation and
-# not an ICD enabled implementation
-if with_gallium_opencl and not with_opencl_icd
-  install_headers(
-    'CL/cl.h',
-    'CL/cl.hpp',
-    'CL/cl_d3d10.h',
-    'CL/cl_d3d11.h',
-    'CL/cl_dx9_media_sharing.h',
-    'CL/cl_egl.h',
-    'CL/cl_ext.h',
-    'CL/cl_gl.h',
-    'CL/cl_gl_ext.h',
-    'CL/cl_platform.h',
-    'CL/opencl.h',
-    subdir: 'CL'
-  )
-endif
-
-if with_intel_vk
-  install_headers('vulkan/vulkan_intel.h', subdir : 'vulkan')
-endif

include/pci_ids/i965_pci_ids.h

@@ -163,27 +163,19 @@ CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3")
 CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3e)")
 CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3e)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
-CHIPSET(0x3184, glk,     "Intel(R) UHD Graphics 605 (Geminilake)")
-CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
+CHIPSET(0x3184, glk,     "Intel(R) HD Graphics (Geminilake)")
+CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
 CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
-CHIPSET(0x3E9A, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
-CHIPSET(0x3EA0, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
-CHIPSET(0x3EA3, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
-CHIPSET(0x3EA9, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
-CHIPSET(0x3EA2, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
-CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
 CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
 CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
 CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
 CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
 CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
 CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")

include/pci_ids/radeonsi_pci_ids.h

@@ -1,229 +1,229 @@
-CHIPSET(0x6780, TAHITI)
-CHIPSET(0x6784, TAHITI)
-CHIPSET(0x6788, TAHITI)
-CHIPSET(0x678A, TAHITI)
-CHIPSET(0x6790, TAHITI)
-CHIPSET(0x6791, TAHITI)
-CHIPSET(0x6792, TAHITI)
-CHIPSET(0x6798, TAHITI)
-CHIPSET(0x6799, TAHITI)
-CHIPSET(0x679A, TAHITI)
-CHIPSET(0x679B, TAHITI)
-CHIPSET(0x679E, TAHITI)
-CHIPSET(0x679F, TAHITI)
+CHIPSET(0x6780, TAHITI_6780, TAHITI)
+CHIPSET(0x6784, TAHITI_6784, TAHITI)
+CHIPSET(0x6788, TAHITI_6788, TAHITI)
+CHIPSET(0x678A, TAHITI_678A, TAHITI)
+CHIPSET(0x6790, TAHITI_6790, TAHITI)
+CHIPSET(0x6791, TAHITI_6791, TAHITI)
+CHIPSET(0x6792, TAHITI_6792, TAHITI)
+CHIPSET(0x6798, TAHITI_6798, TAHITI)
+CHIPSET(0x6799, TAHITI_6799, TAHITI)
+CHIPSET(0x679A, TAHITI_679A, TAHITI)
+CHIPSET(0x679B, TAHITI_679B, TAHITI)
+CHIPSET(0x679E, TAHITI_679E, TAHITI)
+CHIPSET(0x679F, TAHITI_679F, TAHITI)
 
-CHIPSET(0x6800, PITCAIRN)
-CHIPSET(0x6801, PITCAIRN)
-CHIPSET(0x6802, PITCAIRN)
-CHIPSET(0x6806, PITCAIRN)
-CHIPSET(0x6808, PITCAIRN)
-CHIPSET(0x6809, PITCAIRN)
-CHIPSET(0x6810, PITCAIRN)
-CHIPSET(0x6811, PITCAIRN)
-CHIPSET(0x6816, PITCAIRN)
-CHIPSET(0x6817, PITCAIRN)
-CHIPSET(0x6818, PITCAIRN)
-CHIPSET(0x6819, PITCAIRN)
-CHIPSET(0x684C, PITCAIRN)
+CHIPSET(0x6800, PITCAIRN_6800, PITCAIRN)
+CHIPSET(0x6801, PITCAIRN_6801, PITCAIRN)
+CHIPSET(0x6802, PITCAIRN_6802, PITCAIRN)
+CHIPSET(0x6806, PITCAIRN_6806, PITCAIRN)
+CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN)
+CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN)
+CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN)
+CHIPSET(0x6811, PITCAIRN_6811, PITCAIRN)
+CHIPSET(0x6816, PITCAIRN_6816, PITCAIRN)
+CHIPSET(0x6817, PITCAIRN_6817, PITCAIRN)
+CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN)
+CHIPSET(0x6819, PITCAIRN_6819, PITCAIRN)
+CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN)
 
-CHIPSET(0x6820, VERDE)
-CHIPSET(0x6821, VERDE)
-CHIPSET(0x6822, VERDE)
-CHIPSET(0x6823, VERDE)
-CHIPSET(0x6824, VERDE)
-CHIPSET(0x6825, VERDE)
-CHIPSET(0x6826, VERDE)
-CHIPSET(0x6827, VERDE)
-CHIPSET(0x6828, VERDE)
-CHIPSET(0x6829, VERDE)
-CHIPSET(0x682A, VERDE)
-CHIPSET(0x682B, VERDE)
-CHIPSET(0x682C, VERDE)
-CHIPSET(0x682D, VERDE)
-CHIPSET(0x682F, VERDE)
-CHIPSET(0x6830, VERDE)
-CHIPSET(0x6831, VERDE)
-CHIPSET(0x6835, VERDE)
-CHIPSET(0x6837, VERDE)
-CHIPSET(0x6838, VERDE)
-CHIPSET(0x6839, VERDE)
-CHIPSET(0x683B, VERDE)
-CHIPSET(0x683D, VERDE)
-CHIPSET(0x683F, VERDE)
+CHIPSET(0x6820, VERDE_6820, VERDE)
+CHIPSET(0x6821, VERDE_6821, VERDE)
+CHIPSET(0x6822, VERDE_6822, VERDE)
+CHIPSET(0x6823, VERDE_6823, VERDE)
+CHIPSET(0x6824, VERDE_6824, VERDE)
+CHIPSET(0x6825, VERDE_6825, VERDE)
+CHIPSET(0x6826, VERDE_6826, VERDE)
+CHIPSET(0x6827, VERDE_6827, VERDE)
+CHIPSET(0x6828, VERDE_6828, VERDE)
+CHIPSET(0x6829, VERDE_6829, VERDE)
+CHIPSET(0x682A, VERDE_682A, VERDE)
+CHIPSET(0x682B, VERDE_682B, VERDE)
+CHIPSET(0x682C, VERDE_682C, VERDE)
+CHIPSET(0x682D, VERDE_682D, VERDE)
+CHIPSET(0x682F, VERDE_682F, VERDE)
+CHIPSET(0x6830, VERDE_6830, VERDE)
+CHIPSET(0x6831, VERDE_6831, VERDE)
+CHIPSET(0x6835, VERDE_6835, VERDE)
+CHIPSET(0x6837, VERDE_6837, VERDE)
+CHIPSET(0x6838, VERDE_6838, VERDE)
+CHIPSET(0x6839, VERDE_6839, VERDE)
+CHIPSET(0x683B, VERDE_683B, VERDE)
+CHIPSET(0x683D, VERDE_683D, VERDE)
+CHIPSET(0x683F, VERDE_683F, VERDE)
 
-CHIPSET(0x6600, OLAND)
-CHIPSET(0x6601, OLAND)
-CHIPSET(0x6602, OLAND)
-CHIPSET(0x6603, OLAND)
-CHIPSET(0x6604, OLAND)
-CHIPSET(0x6605, OLAND)
-CHIPSET(0x6606, OLAND)
-CHIPSET(0x6607, OLAND)
-CHIPSET(0x6608, OLAND)
-CHIPSET(0x6610, OLAND)
-CHIPSET(0x6611, OLAND)
-CHIPSET(0x6613, OLAND)
-CHIPSET(0x6617, OLAND)
-CHIPSET(0x6620, OLAND)
-CHIPSET(0x6621, OLAND)
-CHIPSET(0x6623, OLAND)
-CHIPSET(0x6631, OLAND)
+CHIPSET(0x6600, OLAND_6600, OLAND)
+CHIPSET(0x6601, OLAND_6601, OLAND)
+CHIPSET(0x6602, OLAND_6602, OLAND)
+CHIPSET(0x6603, OLAND_6603, OLAND)
+CHIPSET(0x6604, OLAND_6604, OLAND)
+CHIPSET(0x6605, OLAND_6605, OLAND)
+CHIPSET(0x6606, OLAND_6606, OLAND)
+CHIPSET(0x6607, OLAND_6607, OLAND)
+CHIPSET(0x6608, OLAND_6608, OLAND)
+CHIPSET(0x6610, OLAND_6610, OLAND)
+CHIPSET(0x6611, OLAND_6611, OLAND)
+CHIPSET(0x6613, OLAND_6613, OLAND)
+CHIPSET(0x6617, OLAND_6617, OLAND)
+CHIPSET(0x6620, OLAND_6620, OLAND)
+CHIPSET(0x6621, OLAND_6621, OLAND)
+CHIPSET(0x6623, OLAND_6623, OLAND)
+CHIPSET(0x6631, OLAND_6631, OLAND)
 
-CHIPSET(0x6660, HAINAN)
-CHIPSET(0x6663, HAINAN)
-CHIPSET(0x6664, HAINAN)
-CHIPSET(0x6665, HAINAN)
-CHIPSET(0x6667, HAINAN)
-CHIPSET(0x666F, HAINAN)
+CHIPSET(0x6660, HAINAN_6660, HAINAN)
+CHIPSET(0x6663, HAINAN_6663, HAINAN)
+CHIPSET(0x6664, HAINAN_6664, HAINAN)
+CHIPSET(0x6665, HAINAN_6665, HAINAN)
+CHIPSET(0x6667, HAINAN_6667, HAINAN)
+CHIPSET(0x666F, HAINAN_666F, HAINAN)
 
-CHIPSET(0x6640, BONAIRE)
-CHIPSET(0x6641, BONAIRE)
-CHIPSET(0x6646, BONAIRE)
-CHIPSET(0x6647, BONAIRE)
-CHIPSET(0x6649, BONAIRE)
-CHIPSET(0x6650, BONAIRE)
-CHIPSET(0x6651, BONAIRE)
-CHIPSET(0x6658, BONAIRE)
-CHIPSET(0x665C, BONAIRE)
-CHIPSET(0x665D, BONAIRE)
-CHIPSET(0x665F, BONAIRE)
+CHIPSET(0x6640, BONAIRE_6640, BONAIRE)
+CHIPSET(0x6641, BONAIRE_6641, BONAIRE)
+CHIPSET(0x6646, BONAIRE_6646, BONAIRE)
+CHIPSET(0x6647, BONAIRE_6647, BONAIRE)
+CHIPSET(0x6649, BONAIRE_6649, BONAIRE)
+CHIPSET(0x6650, BONAIRE_6650, BONAIRE)
+CHIPSET(0x6651, BONAIRE_6651, BONAIRE)
+CHIPSET(0x6658, BONAIRE_6658, BONAIRE)
+CHIPSET(0x665C, BONAIRE_665C, BONAIRE)
+CHIPSET(0x665D, BONAIRE_665D, BONAIRE)
+CHIPSET(0x665F, BONAIRE_665F, BONAIRE)
 
-CHIPSET(0x9830, KABINI)
-CHIPSET(0x9831, KABINI)
-CHIPSET(0x9832, KABINI)
-CHIPSET(0x9833, KABINI)
-CHIPSET(0x9834, KABINI)
-CHIPSET(0x9835, KABINI)
-CHIPSET(0x9836, KABINI)
-CHIPSET(0x9837, KABINI)
-CHIPSET(0x9838, KABINI)
-CHIPSET(0x9839, KABINI)
-CHIPSET(0x983A, KABINI)
-CHIPSET(0x983B, KABINI)
-CHIPSET(0x983C, KABINI)
-CHIPSET(0x983D, KABINI)
-CHIPSET(0x983E, KABINI)
-CHIPSET(0x983F, KABINI)
+CHIPSET(0x9830, KABINI_9830, KABINI)
+CHIPSET(0x9831, KABINI_9831, KABINI)
+CHIPSET(0x9832, KABINI_9832, KABINI)
+CHIPSET(0x9833, KABINI_9833, KABINI)
+CHIPSET(0x9834, KABINI_9834, KABINI)
+CHIPSET(0x9835, KABINI_9835, KABINI)
+CHIPSET(0x9836, KABINI_9836, KABINI)
+CHIPSET(0x9837, KABINI_9837, KABINI)
+CHIPSET(0x9838, KABINI_9838, KABINI)
+CHIPSET(0x9839, KABINI_9839, KABINI)
+CHIPSET(0x983A, KABINI_983A, KABINI)
+CHIPSET(0x983B, KABINI_983B, KABINI)
+CHIPSET(0x983C, KABINI_983C, KABINI)
+CHIPSET(0x983D, KABINI_983D, KABINI)
+CHIPSET(0x983E, KABINI_983E, KABINI)
+CHIPSET(0x983F, KABINI_983F, KABINI)
 
-CHIPSET(0x9850, MULLINS)
-CHIPSET(0x9851, MULLINS)
-CHIPSET(0x9852, MULLINS)
-CHIPSET(0x9853, MULLINS)
-CHIPSET(0x9854, MULLINS)
-CHIPSET(0x9855, MULLINS)
-CHIPSET(0x9856, MULLINS)
-CHIPSET(0x9857, MULLINS)
-CHIPSET(0x9858, MULLINS)
-CHIPSET(0x9859, MULLINS)
-CHIPSET(0x985A, MULLINS)
-CHIPSET(0x985B, MULLINS)
-CHIPSET(0x985C, MULLINS)
-CHIPSET(0x985D, MULLINS)
-CHIPSET(0x985E, MULLINS)
-CHIPSET(0x985F, MULLINS)
+CHIPSET(0x9850, MULLINS_9850, MULLINS)
+CHIPSET(0x9851, MULLINS_9851, MULLINS)
+CHIPSET(0x9852, MULLINS_9852, MULLINS)
+CHIPSET(0x9853, MULLINS_9853, MULLINS)
+CHIPSET(0x9854, MULLINS_9854, MULLINS)
+CHIPSET(0x9855, MULLINS_9855, MULLINS)
+CHIPSET(0x9856, MULLINS_9856, MULLINS)
+CHIPSET(0x9857, MULLINS_9857, MULLINS)
+CHIPSET(0x9858, MULLINS_9858, MULLINS)
+CHIPSET(0x9859, MULLINS_9859, MULLINS)
+CHIPSET(0x985A, MULLINS_985A, MULLINS)
+CHIPSET(0x985B, MULLINS_985B, MULLINS)
+CHIPSET(0x985C, MULLINS_985C, MULLINS)
+CHIPSET(0x985D, MULLINS_985D, MULLINS)
+CHIPSET(0x985E, MULLINS_985E, MULLINS)
+CHIPSET(0x985F, MULLINS_985F, MULLINS)
 
-CHIPSET(0x1304, KAVERI)
-CHIPSET(0x1305, KAVERI)
-CHIPSET(0x1306, KAVERI)
-CHIPSET(0x1307, KAVERI)
-CHIPSET(0x1309, KAVERI)
-CHIPSET(0x130A, KAVERI)
-CHIPSET(0x130B, KAVERI)
-CHIPSET(0x130C, KAVERI)
-CHIPSET(0x130D, KAVERI)
-CHIPSET(0x130E, KAVERI)
-CHIPSET(0x130F, KAVERI)
-CHIPSET(0x1310, KAVERI)
-CHIPSET(0x1311, KAVERI)
-CHIPSET(0x1312, KAVERI)
-CHIPSET(0x1313, KAVERI)
-CHIPSET(0x1315, KAVERI)
-CHIPSET(0x1316, KAVERI)
-CHIPSET(0x1317, KAVERI)
-CHIPSET(0x1318, KAVERI)
-CHIPSET(0x131B, KAVERI)
-CHIPSET(0x131C, KAVERI)
-CHIPSET(0x131D, KAVERI)
+CHIPSET(0x1304, KAVERI_1304, KAVERI)
+CHIPSET(0x1305, KAVERI_1305, KAVERI)
+CHIPSET(0x1306, KAVERI_1306, KAVERI)
+CHIPSET(0x1307, KAVERI_1307, KAVERI)
+CHIPSET(0x1309, KAVERI_1309, KAVERI)
+CHIPSET(0x130A, KAVERI_130A, KAVERI)
+CHIPSET(0x130B, KAVERI_130B, KAVERI)
+CHIPSET(0x130C, KAVERI_130C, KAVERI)
+CHIPSET(0x130D, KAVERI_130D, KAVERI)
+CHIPSET(0x130E, KAVERI_130E, KAVERI)
+CHIPSET(0x130F, KAVERI_130F, KAVERI)
+CHIPSET(0x1310, KAVERI_1310, KAVERI)
+CHIPSET(0x1311, KAVERI_1311, KAVERI)
+CHIPSET(0x1312, KAVERI_1312, KAVERI)
+CHIPSET(0x1313, KAVERI_1313, KAVERI)
+CHIPSET(0x1315, KAVERI_1315, KAVERI)
+CHIPSET(0x1316, KAVERI_1316, KAVERI)
+CHIPSET(0x1317, KAVERI_1317, KAVERI)
+CHIPSET(0x1318, KAVERI_1318, KAVERI)
+CHIPSET(0x131B, KAVERI_131B, KAVERI)
+CHIPSET(0x131C, KAVERI_131C, KAVERI)
+CHIPSET(0x131D, KAVERI_131D, KAVERI)
 
-CHIPSET(0x67A0, HAWAII)
-CHIPSET(0x67A1, HAWAII)
-CHIPSET(0x67A2, HAWAII)
-CHIPSET(0x67A8, HAWAII)
-CHIPSET(0x67A9, HAWAII)
-CHIPSET(0x67AA, HAWAII)
-CHIPSET(0x67B0, HAWAII)
-CHIPSET(0x67B1, HAWAII)
-CHIPSET(0x67B8, HAWAII)
-CHIPSET(0x67B9, HAWAII)
-CHIPSET(0x67BA, HAWAII)
-CHIPSET(0x67BE, HAWAII)
+CHIPSET(0x67A0, HAWAII_67A0, HAWAII)
+CHIPSET(0x67A1, HAWAII_67A1, HAWAII)
+CHIPSET(0x67A2, HAWAII_67A2, HAWAII)
+CHIPSET(0x67A8, HAWAII_67A8, HAWAII)
+CHIPSET(0x67A9, HAWAII_67A9, HAWAII)
+CHIPSET(0x67AA, HAWAII_67AA, HAWAII)
+CHIPSET(0x67B0, HAWAII_67B0, HAWAII)
+CHIPSET(0x67B1, HAWAII_67B1, HAWAII)
+CHIPSET(0x67B8, HAWAII_67B8, HAWAII)
+CHIPSET(0x67B9, HAWAII_67B9, HAWAII)
+CHIPSET(0x67BA, HAWAII_67BA, HAWAII)
+CHIPSET(0x67BE, HAWAII_67BE, HAWAII)
 
-CHIPSET(0x6900, ICELAND)
-CHIPSET(0x6901, ICELAND)
-CHIPSET(0x6902, ICELAND)
-CHIPSET(0x6903, ICELAND)
-CHIPSET(0x6907, ICELAND)
+CHIPSET(0x6900, ICELAND_, ICELAND)
+CHIPSET(0x6901, ICELAND_, ICELAND)
+CHIPSET(0x6902, ICELAND_, ICELAND)
+CHIPSET(0x6903, ICELAND_, ICELAND)
+CHIPSET(0x6907, ICELAND_, ICELAND)
 
-CHIPSET(0x6920, TONGA)
-CHIPSET(0x6921, TONGA)
-CHIPSET(0x6928, TONGA)
-CHIPSET(0x6929, TONGA)
-CHIPSET(0x692B, TONGA)
-CHIPSET(0x692F, TONGA)
-CHIPSET(0x6930, TONGA)
-CHIPSET(0x6938, TONGA)
-CHIPSET(0x6939, TONGA)
+CHIPSET(0x6920, TONGA_, TONGA)
+CHIPSET(0x6921, TONGA_, TONGA)
+CHIPSET(0x6928, TONGA_, TONGA)
+CHIPSET(0x6929, TONGA_, TONGA)
+CHIPSET(0x692B, TONGA_, TONGA)
+CHIPSET(0x692F, TONGA_, TONGA)
+CHIPSET(0x6930, TONGA_, TONGA)
+CHIPSET(0x6938, TONGA_, TONGA)
+CHIPSET(0x6939, TONGA_, TONGA)
 
-CHIPSET(0x9870, CARRIZO)
-CHIPSET(0x9874, CARRIZO)
-CHIPSET(0x9875, CARRIZO)
-CHIPSET(0x9876, CARRIZO)
-CHIPSET(0x9877, CARRIZO)
+CHIPSET(0x9870, CARRIZO_, CARRIZO)
+CHIPSET(0x9874, CARRIZO_, CARRIZO)
+CHIPSET(0x9875, CARRIZO_, CARRIZO)
+CHIPSET(0x9876, CARRIZO_, CARRIZO)
+CHIPSET(0x9877, CARRIZO_, CARRIZO)
 
-CHIPSET(0x7300, FIJI)
+CHIPSET(0x7300, FIJI_, FIJI)
 
-CHIPSET(0x67E0, POLARIS11)
-CHIPSET(0x67E1, POLARIS11)
-CHIPSET(0x67E3, POLARIS11)
-CHIPSET(0x67E7, POLARIS11)
-CHIPSET(0x67E8, POLARIS11)
-CHIPSET(0x67E9, POLARIS11)
-CHIPSET(0x67EB, POLARIS11)
-CHIPSET(0x67EF, POLARIS11)
-CHIPSET(0x67FF, POLARIS11)
+CHIPSET(0x67E0, POLARIS11_, POLARIS11)
+CHIPSET(0x67E1, POLARIS11_, POLARIS11)
+CHIPSET(0x67E3, POLARIS11_, POLARIS11)
+CHIPSET(0x67E7, POLARIS11_, POLARIS11)
+CHIPSET(0x67E8, POLARIS11_, POLARIS11)
+CHIPSET(0x67E9, POLARIS11_, POLARIS11)
+CHIPSET(0x67EB, POLARIS11_, POLARIS11)
+CHIPSET(0x67EF, POLARIS11_, POLARIS11)
+CHIPSET(0x67FF, POLARIS11_, POLARIS11)
 
-CHIPSET(0x67C0, POLARIS10)
-CHIPSET(0x67C1, POLARIS10)
-CHIPSET(0x67C2, POLARIS10)
-CHIPSET(0x67C4, POLARIS10)
-CHIPSET(0x67C7, POLARIS10)
-CHIPSET(0x67C8, POLARIS10)
-CHIPSET(0x67C9, POLARIS10)
-CHIPSET(0x67CA, POLARIS10)
-CHIPSET(0x67CC, POLARIS10)
-CHIPSET(0x67CF, POLARIS10)
-CHIPSET(0x67D0, POLARIS10)
-CHIPSET(0x67DF, POLARIS10)
+CHIPSET(0x67C0, POLARIS10_, POLARIS10)
+CHIPSET(0x67C1, POLARIS10_, POLARIS10)
+CHIPSET(0x67C2, POLARIS10_, POLARIS10)
+CHIPSET(0x67C4, POLARIS10_, POLARIS10)
+CHIPSET(0x67C7, POLARIS10_, POLARIS10)
+CHIPSET(0x67C8, POLARIS10_, POLARIS10)
+CHIPSET(0x67C9, POLARIS10_, POLARIS10)
+CHIPSET(0x67CA, POLARIS10_, POLARIS10)
+CHIPSET(0x67CC, POLARIS10_, POLARIS10)
+CHIPSET(0x67CF, POLARIS10_, POLARIS10)
+CHIPSET(0x67D0, POLARIS10_, POLARIS10)
+CHIPSET(0x67DF, POLARIS10_, POLARIS10)
 
-CHIPSET(0x98E4, STONEY)
+CHIPSET(0x98E4, STONEY_, STONEY)
 
-CHIPSET(0x6980, POLARIS12)
-CHIPSET(0x6981, POLARIS12)
-CHIPSET(0x6985, POLARIS12)
-CHIPSET(0x6986, POLARIS12)
-CHIPSET(0x6987, POLARIS12)
-CHIPSET(0x6995, POLARIS12)
-CHIPSET(0x6997, POLARIS12)
-CHIPSET(0x699F, POLARIS12)
+CHIPSET(0x6980, POLARIS12_, POLARIS12)
+CHIPSET(0x6981, POLARIS12_, POLARIS12)
+CHIPSET(0x6985, POLARIS12_, POLARIS12)
+CHIPSET(0x6986, POLARIS12_, POLARIS12)
+CHIPSET(0x6987, POLARIS12_, POLARIS12)
+CHIPSET(0x6995, POLARIS12_, POLARIS12)
+CHIPSET(0x6997, POLARIS12_, POLARIS12)
+CHIPSET(0x699F, POLARIS12_, POLARIS12)
 
-CHIPSET(0x6860, VEGA10)
-CHIPSET(0x6861, VEGA10)
-CHIPSET(0x6862, VEGA10)
-CHIPSET(0x6863, VEGA10)
-CHIPSET(0x6864, VEGA10)
-CHIPSET(0x6867, VEGA10)
-CHIPSET(0x6868, VEGA10)
-CHIPSET(0x687F, VEGA10)
-CHIPSET(0x686C, VEGA10)
+CHIPSET(0x6860, VEGA10_, VEGA10)
+CHIPSET(0x6861, VEGA10_, VEGA10)
+CHIPSET(0x6862, VEGA10_, VEGA10)
+CHIPSET(0x6863, VEGA10_, VEGA10)
+CHIPSET(0x6864, VEGA10_, VEGA10)
+CHIPSET(0x6867, VEGA10_, VEGA10)
+CHIPSET(0x6868, VEGA10_, VEGA10)
+CHIPSET(0x687F, VEGA10_, VEGA10)
+CHIPSET(0x686C, VEGA10_, VEGA10)
 
-CHIPSET(0x15DD, RAVEN)
+CHIPSET(0x15DD, RAVEN_, RAVEN)

include/vulkan/vulkan.h

@@ -43,7 +43,7 @@ extern "C" {
 #define VK_VERSION_MINOR(version) (((uint32_t)(version) >> 12) & 0x3ff)
 #define VK_VERSION_PATCH(version) ((uint32_t)(version) & 0xfff)
 // Version of this file
-#define VK_HEADER_VERSION 66
+#define VK_HEADER_VERSION 63
 
 
 #define VK_NULL_HANDLE 0
@@ -355,9 +355,6 @@ typedef enum VkStructureType {
     VK_STRUCTURE_TYPE_VALIDATION_CACHE_CREATE_INFO_EXT = 1000160000,
     VK_STRUCTURE_TYPE_SHADER_MODULE_VALIDATION_CACHE_CREATE_INFO_EXT = 1000160001,
     VK_STRUCTURE_TYPE_DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT = 1000174000,
-    VK_STRUCTURE_TYPE_IMPORT_MEMORY_HOST_POINTER_INFO_EXT = 1000178000,
-    VK_STRUCTURE_TYPE_MEMORY_HOST_POINTER_PROPERTIES_EXT = 1000178001,
-    VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT = 1000178002,
     VK_STRUCTURE_TYPE_BEGIN_RANGE = VK_STRUCTURE_TYPE_APPLICATION_INFO,
     VK_STRUCTURE_TYPE_END_RANGE = VK_STRUCTURE_TYPE_LOADER_DEVICE_CREATE_INFO,
     VK_STRUCTURE_TYPE_RANGE_SIZE = (VK_STRUCTURE_TYPE_LOADER_DEVICE_CREATE_INFO - VK_STRUCTURE_TYPE_APPLICATION_INFO + 1),
@@ -4198,9 +4195,6 @@ typedef enum VkExternalMemoryHandleTypeFlagBitsKHR {
     VK_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_TEXTURE_KMT_BIT_KHR = 0x00000010,
     VK_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP_BIT_KHR = 0x00000020,
     VK_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE_BIT_KHR = 0x00000040,
-    VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT = 0x00000200,
-    VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT = 0x00000080,
-    VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_MAPPED_FOREIGN_MEMORY_BIT_EXT = 0x00000100,
     VK_EXTERNAL_MEMORY_HANDLE_TYPE_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
 } VkExternalMemoryHandleTypeFlagBitsKHR;
 typedef VkFlags VkExternalMemoryHandleTypeFlagsKHR;
@@ -5200,7 +5194,7 @@ VKAPI_ATTR VkResult VKAPI_CALL vkBindImageMemory2KHR(
 #define VK_EXT_debug_report 1
 VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkDebugReportCallbackEXT)
 
-#define VK_EXT_DEBUG_REPORT_SPEC_VERSION  9
+#define VK_EXT_DEBUG_REPORT_SPEC_VERSION  8
 #define VK_EXT_DEBUG_REPORT_EXTENSION_NAME "VK_EXT_debug_report"
 #define VK_STRUCTURE_TYPE_DEBUG_REPORT_CREATE_INFO_EXT VK_STRUCTURE_TYPE_DEBUG_REPORT_CALLBACK_CREATE_INFO_EXT
 #define VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_EXT VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT
@@ -5494,52 +5488,6 @@ typedef struct VkTextureLODGatherFormatPropertiesAMD {
 
 
 
-#define VK_AMD_shader_info 1
-#define VK_AMD_SHADER_INFO_SPEC_VERSION   1
-#define VK_AMD_SHADER_INFO_EXTENSION_NAME "VK_AMD_shader_info"
-
-
-typedef enum VkShaderInfoTypeAMD {
-    VK_SHADER_INFO_TYPE_STATISTICS_AMD = 0,
-    VK_SHADER_INFO_TYPE_BINARY_AMD = 1,
-    VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD = 2,
-    VK_SHADER_INFO_TYPE_BEGIN_RANGE_AMD = VK_SHADER_INFO_TYPE_STATISTICS_AMD,
-    VK_SHADER_INFO_TYPE_END_RANGE_AMD = VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD,
-    VK_SHADER_INFO_TYPE_RANGE_SIZE_AMD = (VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD - VK_SHADER_INFO_TYPE_STATISTICS_AMD + 1),
-    VK_SHADER_INFO_TYPE_MAX_ENUM_AMD = 0x7FFFFFFF
-} VkShaderInfoTypeAMD;
-
-typedef struct VkShaderResourceUsageAMD {
-    uint32_t    numUsedVgprs;
-    uint32_t    numUsedSgprs;
-    uint32_t    ldsSizePerLocalWorkGroup;
-    size_t      ldsUsageSizeInBytes;
-    size_t      scratchMemUsageInBytes;
-} VkShaderResourceUsageAMD;
-
-typedef struct VkShaderStatisticsInfoAMD {
-    VkShaderStageFlags          shaderStageMask;
-    VkShaderResourceUsageAMD    resourceUsage;
-    uint32_t                    numPhysicalVgprs;
-    uint32_t                    numPhysicalSgprs;
-    uint32_t                    numAvailableVgprs;
-    uint32_t                    numAvailableSgprs;
-    uint32_t                    computeWorkGroupSize[3];
-} VkShaderStatisticsInfoAMD;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkGetShaderInfoAMD)(VkDevice device, VkPipeline pipeline, VkShaderStageFlagBits shaderStage, VkShaderInfoTypeAMD infoType, size_t* pInfoSize, void* pInfo);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkGetShaderInfoAMD(
-    VkDevice                                    device,
-    VkPipeline                                  pipeline,
-    VkShaderStageFlagBits                       shaderStage,
-    VkShaderInfoTypeAMD                         infoType,
-    size_t*                                     pInfoSize,
-    void*                                       pInfo);
-#endif
-
 #define VK_AMD_shader_image_load_store_lod 1
 #define VK_AMD_SHADER_IMAGE_LOAD_STORE_LOD_SPEC_VERSION 1
 #define VK_AMD_SHADER_IMAGE_LOAD_STORE_LOD_EXTENSION_NAME "VK_AMD_shader_image_load_store_lod"
@@ -6622,17 +6570,6 @@ VKAPI_ATTR VkResult VKAPI_CALL vkCreateMacOSSurfaceMVK(
 #endif
 #endif /* VK_USE_PLATFORM_MACOS_MVK */
 
-#define VK_EXT_external_memory_dma_buf 1
-#define VK_EXT_EXTERNAL_MEMORY_DMA_BUF_SPEC_VERSION 1
-#define VK_EXT_EXTERNAL_MEMORY_DMA_BUF_EXTENSION_NAME "VK_EXT_external_memory_dma_buf"
-
-
-#define VK_EXT_queue_family_foreign 1
-#define VK_EXT_QUEUE_FAMILY_FOREIGN_SPEC_VERSION 1
-#define VK_EXT_QUEUE_FAMILY_FOREIGN_EXTENSION_NAME "VK_EXT_queue_family_foreign"
-#define VK_QUEUE_FAMILY_FOREIGN_EXT       (~0U-2)
-
-
 #define VK_EXT_sampler_filter_minmax 1
 #define VK_EXT_SAMPLER_FILTER_MINMAX_SPEC_VERSION 1
 #define VK_EXT_SAMPLER_FILTER_MINMAX_EXTENSION_NAME "VK_EXT_sampler_filter_minmax"
@@ -6924,18 +6861,18 @@ VKAPI_ATTR VkResult VKAPI_CALL vkGetValidationCacheDataEXT(
 
 
 #define VK_EXT_global_priority 1
-#define VK_EXT_GLOBAL_PRIORITY_SPEC_VERSION 2
+#define VK_EXT_GLOBAL_PRIORITY_SPEC_VERSION 1
 #define VK_EXT_GLOBAL_PRIORITY_EXTENSION_NAME "VK_EXT_global_priority"
 
 
 typedef enum VkQueueGlobalPriorityEXT {
-    VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT = 128,
-    VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT = 256,
-    VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT = 512,
-    VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT = 1024,
-    VK_QUEUE_GLOBAL_PRIORITY_BEGIN_RANGE_EXT = VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT,
-    VK_QUEUE_GLOBAL_PRIORITY_END_RANGE_EXT = VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT,
-    VK_QUEUE_GLOBAL_PRIORITY_RANGE_SIZE_EXT = (VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT - VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT + 1),
+    VK_QUEUE_GLOBAL_PRIORITY_LOW = 128,
+    VK_QUEUE_GLOBAL_PRIORITY_MEDIUM = 256,
+    VK_QUEUE_GLOBAL_PRIORITY_HIGH = 512,
+    VK_QUEUE_GLOBAL_PRIORITY_REALTIME = 1024,
+    VK_QUEUE_GLOBAL_PRIORITY_BEGIN_RANGE_EXT = VK_QUEUE_GLOBAL_PRIORITY_LOW,
+    VK_QUEUE_GLOBAL_PRIORITY_END_RANGE_EXT = VK_QUEUE_GLOBAL_PRIORITY_REALTIME,
+    VK_QUEUE_GLOBAL_PRIORITY_RANGE_SIZE_EXT = (VK_QUEUE_GLOBAL_PRIORITY_REALTIME - VK_QUEUE_GLOBAL_PRIORITY_LOW + 1),
     VK_QUEUE_GLOBAL_PRIORITY_MAX_ENUM_EXT = 0x7FFFFFFF
 } VkQueueGlobalPriorityEXT;
 
@@ -6947,40 +6884,6 @@ typedef struct VkDeviceQueueGlobalPriorityCreateInfoEXT {
 
 
 
-#define VK_EXT_external_memory_host 1
-#define VK_EXT_EXTERNAL_MEMORY_HOST_SPEC_VERSION 1
-#define VK_EXT_EXTERNAL_MEMORY_HOST_EXTENSION_NAME "VK_EXT_external_memory_host"
-
-typedef struct VkImportMemoryHostPointerInfoEXT {
-    VkStructureType                          sType;
-    const void*                              pNext;
-    VkExternalMemoryHandleTypeFlagBitsKHR    handleType;
-    void*                                    pHostPointer;
-} VkImportMemoryHostPointerInfoEXT;
-
-typedef struct VkMemoryHostPointerPropertiesEXT {
-    VkStructureType    sType;
-    void*              pNext;
-    uint32_t           memoryTypeBits;
-} VkMemoryHostPointerPropertiesEXT;
-
-typedef struct VkPhysicalDeviceExternalMemoryHostPropertiesEXT {
-    VkStructureType    sType;
-    void*              pNext;
-    VkDeviceSize       minImportedHostPointerAlignment;
-} VkPhysicalDeviceExternalMemoryHostPropertiesEXT;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkGetMemoryHostPointerPropertiesEXT)(VkDevice device, VkExternalMemoryHandleTypeFlagBitsKHR handleType, const void* pHostPointer, VkMemoryHostPointerPropertiesEXT* pMemoryHostPointerProperties);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkGetMemoryHostPointerPropertiesEXT(
-    VkDevice                                    device,
-    VkExternalMemoryHandleTypeFlagBitsKHR       handleType,
-    const void*                                 pHostPointer,
-    VkMemoryHostPointerPropertiesEXT*           pMemoryHostPointerProperties);
-#endif
-
 #ifdef __cplusplus
 }
 #endif

meson_options.txt

@@ -21,129 +21,45 @@
 option(
   'platforms',
   type : 'string',
-  value : 'auto',
-  description : 'comma separated list of window systems to support. If this is set to auto all platforms applicable to the OS will be enabled.'
+  value : 'x11,wayland,drm,surfaceless',
+  description : 'comma separated list of window systems to support. wayland, x11, surfaceless, drm, etc.'
 )
 option(
   'dri3',
   type : 'combo',
   value : 'auto',
-  choices : ['auto', 'true', 'false'],
+  choices : ['auto', 'yes', 'no'],
   description : 'enable support for dri3'
 )
 option(
   'dri-drivers',
   type : 'string',
-  value : 'auto',
-  description : 'comma separated list of dri drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
+  value : 'i915,i965',
+  description : 'comma separated list of dri drivers to build.'
 )
 option(
   'dri-drivers-path',
   type : 'string',
   value : '',
-  description : 'Location to install dri drivers. Default: $libdir/dri.'
-)
-option(
-  'dri-search-path',
-  type : 'string',
-  value : '',
-  description : 'Locations to search for dri drivers, passed as colon separated list. Default: dri-drivers-path.'
+  description : 'Location of dri drivers. Default: $libdir/dri.'
 )
 option(
   'gallium-drivers',
   type : 'string',
-  value : 'auto',
-  description : 'comma separated list of gallium drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
+  value : 'pl111,radeonsi,nouveau,swrast,vc4',
+  description : 'comma separated list of gallium drivers to build.'
 )
 option(
-  'gallium-extra-hud',
-  type : 'boolean',
-  value : false,
-  description : 'Enable HUD block/NIC I/O HUD status support',
-)
-option(
-  'gallium-vdpau',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'enable gallium vdpau state tracker.',
-)
-option(
-  'vdpau-libs-path',
+  'gallium-media',
   type : 'string',
   value : '',
-  description : 'path to put vdpau libraries. defaults to $libdir/vdpau.'
-)
-option(
-  'gallium-xvmc',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'enable gallium xvmc state tracker.',
-)
-option(
-  'xvmc-libs-path',
-  type : 'string',
-  value : '',
-  description : 'path to put xvmc libraries. defaults to $libdir.'
-)
-option(
-  'gallium-omx',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'enable gallium omx bellagio state tracker.',
-)
-option(
-  'omx-libs-path',
-  type : 'string',
-  value : '',
-  description : 'path to put omx libraries. defaults to omx-bellagio pkg-config pluginsdir.'
-)
-option(
-  'gallium-va',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'enable gallium va state tracker.',
-)
-option(
-  'va-libs-path',
-  type : 'string',
-  value : '',
-  description : 'path to put va libraries. defaults to $libdir/dri.'
-)
-option(
-  'gallium-xa',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'enable gallium xa state tracker.',
-)
-option(
-  'gallium-nine',
-  type : 'boolean',
-  value : false,
-  description : 'build gallium "nine" Direct3D 9.x state tracker.',
-)
-option(
-  'gallium-opencl',
-  type : 'combo',
-  choices : ['icd', 'standalone', 'disabled'],
-  value : 'disabled',
-  description : 'build gallium "clover" OpenCL state tracker.',
-)
-option(
-  'd3d-drivers-path',
-  type : 'string',
-  value : '',
-  description : 'Location of D3D drivers. Default: $libdir/d3d',
+  description : 'comma separated list of gallium media APIs to build (omx,va,vdpau,xvmc).'
 )
 option(
   'vulkan-drivers',
   type : 'string',
-  value : 'auto',
-  description : 'comma separated list of vulkan drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
+  value : 'intel,amd',
+  description : 'comma separated list of vulkan drivers to build.'
 )
 option(
   'shader-cache',
@@ -185,7 +101,7 @@ option(
   'gbm',
   type : 'combo',
   value : 'auto',
-  choices : ['auto', 'true', 'false'],
+  choices : ['auto', 'yes', 'no'],
   description : 'Build support for gbm platform'
 )
 option(
@@ -199,7 +115,7 @@ option(
   'egl',
   type : 'combo',
   value : 'auto',
-  choices : ['auto', 'true', 'false'],
+  choices : ['auto', 'yes', 'no'],
   description : 'Build support for EGL platform'
 )
 option(
@@ -216,31 +132,15 @@ option(
 )
 option(
   'llvm',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
+  type : 'boolean',
+  value : true,
   description : 'Build with LLVM support.'
 )
 option(
   'valgrind',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'Build with valgrind support'
-)
-option(
-  'libunwind',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'Use libunwind for stack-traces'
-)
-option(
-  'lmsensors',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'Enable HUD lmsensors support.'
+  type : 'boolean',
+  value : true,
+  description : 'Build with valgrind support if possible'
 )
 option(
   'build-tests',
@@ -254,29 +154,3 @@ option(
   value : false,
   description : 'Enable floating point textures and renderbuffers. This option may be patent encumbered, please read docs/patents.txt and consult with your lawyer before turning this on.'
 )
-option(
-  'selinux',
-  type : 'boolean',
-  value : false,
-  description : 'Build an SELinux-aware Mesa'
-)
-option(
-  'osmesa',
-  type : 'combo',
-  value : 'none',
-  choices : ['none', 'classic', 'gallium'],
-  description : 'Build OSmesa.'
-)
-option(
-  'osmesa-bits',
-  type : 'combo',
-  value : '8',
-  choices : ['8', '16', '32'],
-  description : 'Number of channel bits for OSMesa.'
-)
-option(
-  'swr-arches',
-  type : 'string',
-  value : 'avx,avx2',
-  description : 'Comma delemited swr architectures. choices : avx,avx2,knl,skx'
-)

scons/gallium.py

@@ -352,15 +352,9 @@ def generate(env):
         if check_header(env, 'xlocale.h'):
             cppdefines += ['HAVE_XLOCALE_H']
 
-        if check_header(env, 'endian.h'):
-            cppdefines += ['HAVE_ENDIAN_H']
-
         if check_functions(env, ['strtod_l', 'strtof_l']):
             cppdefines += ['HAVE_STRTOD_L']
 
-        if check_functions(env, ['timespec_get']):
-            cppdefines += ['HAVE_TIMESPEC_GET']
-
     if platform == 'windows':
         cppdefines += [
             'WIN32',

src/Makefile.am

@@ -19,14 +19,21 @@
 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 # IN THE SOFTWARE.
 
-.PHONY: git_sha1.h
-git_sha1.h: $(top_srcdir)/src/git_sha1.h.in
-	@echo "updating $@"
-	@$(PYTHON2) $(top_srcdir)/bin/git_sha1_gen.py --output $@
+.PHONY: git_sha1.h.tmp
+git_sha1.h.tmp:
+	@$(PYTHON2) $(top_srcdir)/bin/git_sha1_gen.py > $@
+
+git_sha1.h: git_sha1.h.tmp
+	@echo "updating git_sha1.h"
+	@if ! cmp -s git_sha1.h.tmp git_sha1.h; then \
+		mv git_sha1.h.tmp git_sha1.h ;\
+	else \
+		rm git_sha1.h.tmp ;\
+	fi
 
 BUILT_SOURCES = git_sha1.h
 CLEANFILES = $(BUILT_SOURCES)
-EXTRA_DIST = git_sha1.h.in meson.build
+EXTRA_DIST = git_sha1.h.in
 
 SUBDIRS = . gtest util mapi/glapi/gen mapi
 
@@ -57,7 +64,7 @@ endif
 # include only conditionally ?
 SUBDIRS += compiler
 
-## Optionally required by EGL
+## Optionally required by GBM, EGL
 if HAVE_PLATFORM_WAYLAND
 SUBDIRS += egl/wayland/wayland-drm
 endif

src/SConscript

@@ -24,12 +24,22 @@ def write_git_sha1_h_file(filename):
     to retrieve the git hashid and write the header file.  An empty file
     will be created if anything goes wrong."""
 
-    args = [ python_cmd, Dir('#').abspath + '/bin/git_sha1_gen.py', '--output', filename ]
-    try:
-        subprocess.call(args)
-    except:
-        print("Warning: exception in write_git_sha1_h_file()")
-        return
+    tempfile = "git_sha1.h.tmp"
+    with open(tempfile, "w") as f:
+        args = [ python_cmd, Dir('#').abspath + '/bin/git_sha1_gen.py' ]
+        try:
+            subprocess.Popen(args, stdout=f).wait()
+        except:
+            print("Warning: exception in write_git_sha1_h_file()")
+            return
+
+    if not os.path.exists(filename) or not filecmp.cmp(tempfile, filename):
+        # The filename does not exist or it's different from the new file,
+        # so replace old file with new.
+        if os.path.exists(filename):
+            os.remove(filename)
+        os.rename(tempfile, filename)
+    return
 
 
 # Create the git_sha1.h header file

src/amd/Android.addrlib.mk

@@ -30,6 +30,8 @@ LOCAL_MODULE := libmesa_amdgpu_addrlib
 
 LOCAL_SRC_FILES := $(ADDRLIB_FILES)
 
+LOCAL_CFLAGS := -DBRAHMA_BUILD=1
+
 LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src \
 	$(MESA_TOP)/src/amd/common \

src/amd/Makefile.addrlib.am

@@ -22,7 +22,6 @@
 ADDRLIB_LIBS = addrlib/libamdgpu_addrlib.la
 
 addrlib_libamdgpu_addrlib_la_CPPFLAGS = \
-	$(DEFINES) \
 	-I$(top_srcdir)/src/ \
 	-I$(srcdir)/common \
 	-I$(srcdir)/addrlib \
@@ -30,10 +29,11 @@ addrlib_libamdgpu_addrlib_la_CPPFLAGS = \
 	-I$(srcdir)/addrlib/inc/chip/gfx9 \
 	-I$(srcdir)/addrlib/inc/chip/r800 \
 	-I$(srcdir)/addrlib/gfx9/chip \
-	-I$(srcdir)/addrlib/r800/chip
+	-I$(srcdir)/addrlib/r800/chip \
+	-DBRAHMA_BUILD=1
 
 addrlib_libamdgpu_addrlib_la_CXXFLAGS = \
-	$(VISIBILITY_CXXFLAGS) $(CXX11_CXXFLAGS)
+	$(VISIBILITY_CXXFLAGS)
 
 noinst_LTLIBRARIES += $(ADDRLIB_LIBS)
 

src/amd/Makefile.am

@@ -23,13 +23,6 @@ include Makefile.sources
 
 noinst_LTLIBRARIES =
 
+EXTRA_DIST = $(COMMON_HEADER_FILES) common/sid_tables.py
 include Makefile.addrlib.am
 include Makefile.common.am
-
-EXTRA_DIST = \
-     $(COMMON_HEADER_FILES) \
-     common/sid_tables.py \
-     meson.build \
-     addrlib/meson.build \
-     common/meson.build \
-     vulkan/meson.build

src/amd/Makefile.sources

@@ -2,13 +2,13 @@ COMMON_HEADER_FILES = \
 	common/gfx9d.h \
 	common/sid.h \
 	common/amd_family.h \
-	common/amd_kernel_code_t.h
+	common/amd_kernel_code_t.h \
+	common/amdgpu_id.h
 
 ADDRLIB_FILES = \
 	addrlib/addrinterface.cpp \
 	addrlib/addrinterface.h \
 	addrlib/addrtypes.h \
-	addrlib/amdgpu_asic_addr.h \
 	addrlib/core/addrcommon.h \
 	addrlib/core/addrelemlib.cpp \
 	addrlib/core/addrelemlib.h \
@@ -25,8 +25,11 @@ ADDRLIB_FILES = \
 	addrlib/gfx9/coord.h \
 	addrlib/gfx9/gfx9addrlib.cpp \
 	addrlib/gfx9/gfx9addrlib.h \
+	addrlib/gfx9/rbmap.cpp \
+	addrlib/gfx9/rbmap.h \
 	addrlib/inc/chip/gfx9/gfx9_gb_reg.h \
 	addrlib/inc/chip/r800/si_gb_reg.h \
+	addrlib/inc/lnx_common_defs.h \
 	addrlib/r800/chip/si_ci_vi_merged_enum.h \
 	addrlib/r800/ciaddrlib.cpp \
 	addrlib/r800/ciaddrlib.h \
@@ -46,10 +49,7 @@ AMD_COMPILER_FILES = \
 	common/ac_llvm_util.h \
 	common/ac_shader_abi.h \
 	common/ac_shader_info.c \
-	common/ac_shader_info.h \
-	common/ac_shader_util.c \
-	common/ac_shader_util.h
-
+	common/ac_shader_info.h
 
 AMD_NIR_FILES = \
 	common/ac_nir_to_llvm.c \

src/amd/addrlib/addrinterface.cpp

@@ -534,11 +534,11 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
 
     if (pLib != NULL)
     {
-        returnCode = pLib->ComputeDccInfo(pIn, pOut);
+       returnCode = pLib->ComputeDccInfo(pIn, pOut);
     }
     else
     {
-        returnCode = ADDR_ERROR;
+       returnCode = ADDR_ERROR;
     }
 
     return returnCode;

src/amd/addrlib/addrinterface.h

@@ -528,7 +528,7 @@ typedef union _ADDR_SURFACE_FLAGS
         UINT_32 preferEquation       : 1; ///< Return equation index without adjusting tile mode
         UINT_32 matchStencilTileCfg  : 1; ///< Select tile index of stencil as well as depth surface
                                           ///  to make sure they share same tile config parameters
-        UINT_32 reserved             : 2; ///< Reserved bits
+        UINT_32 reserved             : 3; ///< Reserved bits
     };
 
     UINT_32 value;
@@ -714,6 +714,12 @@ typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
         };
         UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
     };
+
+#if ADDR_AM_BUILD // These two fields are not valid in SW blt since no HTILE access
+    UINT_32         addr5Swizzle;       ///< ADDR5_SWIZZLE_MASK of DB_DEPTH_INFO
+    BOOL_32         is32ByteTile;       ///< Caller must have access to HTILE buffer and know if
+                                        ///  this tile is compressed to 32B
+#endif
 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
 
 /**
@@ -851,11 +857,8 @@ typedef union _ADDR_HTILE_FLAGS
 {
     struct
     {
-        UINT_32 tcCompatible          : 1;  ///< Flag indicates surface needs to be shader readable
-        UINT_32 skipTcCompatSizeAlign : 1;  ///< Flag indicates that addrLib will not align htile
-                                            ///  size to 256xBankxPipe when computing tc-compatible
-                                            ///  htile info.
-        UINT_32 reserved              : 30; ///< Reserved bits
+        UINT_32 tcCompatible  : 1; ///< Flag indicates surface needs to be shader readable
+        UINT_32 reserved      :31; ///< Reserved bits
     };
 
     UINT_32 value;
@@ -912,9 +915,6 @@ typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
     UINT_64 sliceSize;          ///< Slice size, in bytes.
     BOOL_32 sliceInterleaved;   ///< Flag to indicate if different slice's htile is interleaved
                                 ///  Compute engine clear can't be used if htile is interleaved
-    BOOL_32 nextMipLevelCompressible;   ///< Flag to indicate whether HTILE can be enabled in
-                                        ///  next mip level, it also indicates if memory set based
-                                        ///  fast clear can be used for current mip level.
 } ADDR_COMPUTE_HTILE_INFO_OUTPUT;
 
 /**
@@ -2188,6 +2188,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
 
 
 
+
 /**
 ****************************************************************************************************
 *   ADDR_PRT_INFO_INPUT
@@ -2232,8 +2233,6 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
     const ADDR_PRT_INFO_INPUT*  pIn,
     ADDR_PRT_INFO_OUTPUT*       pOut);
 
-
-
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     DCC key functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2294,8 +2293,6 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
     const ADDR_COMPUTE_DCCINFO_INPUT*       pIn,
     ADDR_COMPUTE_DCCINFO_OUTPUT*            pOut);
 
-
-
 /**
 ****************************************************************************************************
 *   ADDR_GET_MAX_ALIGNMENTS_OUTPUT
@@ -2696,8 +2693,10 @@ typedef struct _ADDR2_META_MIP_INFO
 
         struct
         {
-            UINT_32    offset;
-            UINT_32    sliceSize;
+            UINT_32    offset;      ///< metadata offset within one slice,
+                                    ///  the thickness of a slice is meta block depth.
+            UINT_32    sliceSize;   ///< metadata size within one slice,
+                                    ///  the thickness of a slice is meta block depth.
         };
     };
 } ADDR2_META_MIP_INFO;
@@ -2721,7 +2720,9 @@ typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
     UINT_32             unalignedHeight;    ///< Depth surface original height (of mip0)
     UINT_32             numSlices;          ///< Number of slices of depth surface (of mip0)
     UINT_32             numMipLevels;       ///< Total mipmap levels of color surface
-    UINT_32             firstMipIdInTail;
+    UINT_32             firstMipIdInTail;   ///< id of the first mip in tail,
+                                            ///  if no mip is in tail, it should be set to
+                                            ///  number of mip levels
 } ADDR2_COMPUTE_HTILE_INFO_INPUT;
 
 /**
@@ -3307,7 +3308,8 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
     UINT_32             numMipLevels;       ///< Total mipmap levels of color surface
     UINT_32             dataSurfaceSize;    ///< The padded size of all slices and mip levels
                                             ///< useful in meta linear case
-    UINT_32             firstMipIdInTail;
+    UINT_32             firstMipIdInTail;   ///< The id of first mip in tail, if no mip is in tail,
+                                            ///  it should be number of mip levels
 } ADDR2_COMPUTE_DCCINFO_INPUT;
 
 /**
@@ -3337,13 +3339,8 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
     UINT_32    metaBlkHeight;      ///< DCC meta block height
     UINT_32    metaBlkDepth;       ///< DCC meta block depth
 
-    UINT_32    metaBlkNumPerSlice; ///< Number of metablock within one slice
-
-    union
-    {
-        UINT_32 fastClearSizePerSlice;  ///< Size of DCC within a slice should be fast cleared
-        UINT_32 dccRamSliceSize;
-    };
+    UINT_32    fastClearSizePerSlice;   ///< Size of DCC within a slice should be fast cleared
+    UINT_32    metaBlkNumPerSlice;      ///< Number of metablock within one slice
 
     ADDR2_META_MIP_INFO* pMipInfo;      ///< DCC mip information
 } ADDR2_COMPUTE_DCCINFO_OUTPUT;
@@ -3574,7 +3571,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
 *   ADDR2_BLOCK_SET
 *
 *   @brief
-*       Bit field that defines block type
+*       Bit field that define block type
 ****************************************************************************************************
 */
 typedef union _ADDR2_BLOCK_SET
@@ -3592,28 +3589,6 @@ typedef union _ADDR2_BLOCK_SET
     UINT_32 value;
 } ADDR2_BLOCK_SET;
 
-/**
-****************************************************************************************************
-*   ADDR2_SWTYPE_SET
-*
-*   @brief
-*       Bit field that defines swizzle type
-****************************************************************************************************
-*/
-typedef union _ADDR2_SWTYPE_SET
-{
-    struct
-    {
-        UINT_32 sw_Z     : 1;   // SW_*_Z_*
-        UINT_32 sw_S     : 1;   // SW_*_S_*
-        UINT_32 sw_D     : 1;   // SW_*_D_*
-        UINT_32 sw_R     : 1;   // SW_*_R_*
-        UINT_32 reserved : 28;
-    };
-
-    UINT_32 value;
-} ADDR2_SWTYPE_SET;
-
 /**
 ****************************************************************************************************
 *   ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
@@ -3632,7 +3607,6 @@ typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
     AddrResrouceLocation  resourceLoction;   ///< Surface heap choice
     ADDR2_BLOCK_SET       forbiddenBlock;    ///< Client can use it to disable some block setting
                                              ///< such as linear for DXTn, tiled for YUV
-    ADDR2_SWTYPE_SET      preferredSwSet;    ///< Client can use it to specify sw type(s) wanted
     BOOL_32               noXor;             ///< Do not use xor mode for this resource
     UINT_32               bpp;               ///< bits per pixel
     UINT_32               width;             ///< Width (of mip0), in pixels
@@ -3658,15 +3632,12 @@ typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
 */
 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
 {
-    UINT_32               size;                 ///< Size of this structure in bytes
+    UINT_32               size;              ///< Size of this structure in bytes
 
-    AddrSwizzleMode       swizzleMode;          ///< Suggested swizzle mode to be used
-    AddrResourceType      resourceType;         ///< Suggested resource type to program HW
-    ADDR2_BLOCK_SET       validBlockSet;        ///< Valid block type bit conbination
-    BOOL_32               canXor;               ///< If client can use xor on a valid macro block
-                                                ///  type
-    ADDR2_SWTYPE_SET      validSwTypeSet;       ///< Valid swizzle type bit combination
-    ADDR2_SWTYPE_SET      clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
+    AddrSwizzleMode       swizzleMode;       ///< Suggested swizzle mode to be used
+    AddrResourceType      resourceType;      ///< Suggested resource type to program HW
+    ADDR2_BLOCK_SET       validBlockSet;     ///< Valid block type bit conbination
+    BOOL_32               canXor;            ///< If client can use xor on a valid macro block type
 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
 
 /**

src/amd/addrlib/amdgpu_asic_addr.h

@@ -1,129 +0,0 @@
-/*
- * Copyright © 2017 Advanced Micro Devices, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
- * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- */
-
-#ifndef _AMDGPU_ASIC_ADDR_H
-#define _AMDGPU_ASIC_ADDR_H
-
-#define ATI_VENDOR_ID         0x1002
-#define AMD_VENDOR_ID         0x1022
-
-// AMDGPU_VENDOR_IS_AMD(vendorId)
-#define AMDGPU_VENDOR_IS_AMD(v) ((v == ATI_VENDOR_ID) || (v == AMD_VENDOR_ID))
-
-#define FAMILY_UNKNOWN 0x00
-#define FAMILY_TN      0x69
-#define FAMILY_SI      0x6E
-#define FAMILY_CI      0x78
-#define FAMILY_KV      0x7D
-#define FAMILY_VI      0x82
-#define FAMILY_POLARIS 0x82
-#define FAMILY_CZ      0x87
-#define FAMILY_AI      0x8D
-#define FAMILY_RV      0x8E
-
-// AMDGPU_FAMILY_IS(familyId, familyName)
-#define FAMILY_IS(f, fn)     (f == FAMILY_##fn)
-#define FAMILY_IS_TN(f)      FAMILY_IS(f, TN)
-#define FAMILY_IS_SI(f)      FAMILY_IS(f, SI)
-#define FAMILY_IS_CI(f)      FAMILY_IS(f, CI)
-#define FAMILY_IS_KV(f)      FAMILY_IS(f, KV)
-#define FAMILY_IS_VI(f)      FAMILY_IS(f, VI)
-#define FAMILY_IS_POLARIS(f) FAMILY_IS(f, POLARIS)
-#define FAMILY_IS_CZ(f)      FAMILY_IS(f, CZ)
-#define FAMILY_IS_AI(f)      FAMILY_IS(f, AI)
-#define FAMILY_IS_RV(f)      FAMILY_IS(f, RV)
-
-#define AMDGPU_UNKNOWN          0xFF
-
-#define AMDGPU_TAHITI_RANGE     0x05, 0x14
-#define AMDGPU_PITCAIRN_RANGE   0x15, 0x28
-#define AMDGPU_CAPEVERDE_RANGE  0x29, 0x3C
-#define AMDGPU_OLAND_RANGE      0x3C, 0x46
-#define AMDGPU_HAINAN_RANGE     0x46, 0xFF
-
-#define AMDGPU_BONAIRE_RANGE    0x14, 0x28
-#define AMDGPU_HAWAII_RANGE     0x28, 0x3C
-
-#define AMDGPU_SPECTRE_RANGE    0x01, 0x41
-#define AMDGPU_SPOOKY_RANGE     0x41, 0x81
-#define AMDGPU_KALINDI_RANGE    0x81, 0xA1
-#define AMDGPU_GODAVARI_RANGE   0xA1, 0xFF
-
-#define AMDGPU_ICELAND_RANGE    0x01, 0x14
-#define AMDGPU_TONGA_RANGE      0x14, 0x28
-#define AMDGPU_FIJI_RANGE       0x3C, 0x50
-
-#define AMDGPU_POLARIS10_RANGE  0x50, 0x5A
-#define AMDGPU_POLARIS11_RANGE  0x5A, 0x64
-#define AMDGPU_POLARIS12_RANGE  0x64, 0x6E
-
-#define AMDGPU_CARRIZO_RANGE    0x01, 0x21
-#define AMDGPU_BRISTOL_RANGE    0x10, 0x21
-#define AMDGPU_STONEY_RANGE     0x61, 0xFF
-
-#define AMDGPU_VEGA10_RANGE     0x01, 0x14
-
-#define AMDGPU_RAVEN_RANGE      0x01, 0x81
-
-#define AMDGPU_EXPAND_FIX(x) x
-#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
-#define AMDGPU_IN_RANGE(val, ...)   AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
-
-
-// ASICREV_IS(eRevisionId, revisionName)
-#define ASICREV_IS(r, rn)              AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE)
-#define ASICREV_IS_TAHITI_P(r)         ASICREV_IS(r, TAHITI)
-#define ASICREV_IS_PITCAIRN_PM(r)      ASICREV_IS(r, PITCAIRN)
-#define ASICREV_IS_CAPEVERDE_M(r)      ASICREV_IS(r, CAPEVERDE)
-#define ASICREV_IS_OLAND_M(r)          ASICREV_IS(r, OLAND)
-#define ASICREV_IS_HAINAN_V(r)         ASICREV_IS(r, HAINAN)
-
-#define ASICREV_IS_BONAIRE_M(r)        ASICREV_IS(r, BONAIRE)
-#define ASICREV_IS_HAWAII_P(r)         ASICREV_IS(r, HAWAII)
-
-#define ASICREV_IS_SPECTRE(r)          ASICREV_IS(r, SPECTRE)
-#define ASICREV_IS_SPOOKY(r)           ASICREV_IS(r, SPOOKY)
-#define ASICREV_IS_KALINDI(r)          ASICREV_IS(r, KALINDI)
-#define ASICREV_IS_KALINDI_GODAVARI(r) ASICREV_IS(r, GODAVARI)
-
-#define ASICREV_IS_ICELAND_M(r)        ASICREV_IS(r, ICELAND)
-#define ASICREV_IS_TONGA_P(r)          ASICREV_IS(r, TONGA)
-#define ASICREV_IS_FIJI_P(r)           ASICREV_IS(r, FIJI)
-
-#define ASICREV_IS_POLARIS10_P(r)      ASICREV_IS(r, POLARIS10)
-#define ASICREV_IS_POLARIS11_M(r)      ASICREV_IS(r, POLARIS11)
-#define ASICREV_IS_POLARIS12_V(r)      ASICREV_IS(r, POLARIS12)
-
-#define ASICREV_IS_CARRIZO(r)          ASICREV_IS(r, CARRIZO)
-#define ASICREV_IS_CARRIZO_BRISTOL(r)  ASICREV_IS(r, BRISTOL)
-#define ASICREV_IS_STONEY(r)           ASICREV_IS(r, STONEY)
-
-#define ASICREV_IS_VEGA10_M(r)         ASICREV_IS(r, VEGA10)
-#define ASICREV_IS_VEGA10_P(r)         ASICREV_IS(r, VEGA10)
-
-#define ASICREV_IS_RAVEN(r)            ASICREV_IS(r, RAVEN)
-
-#endif // _AMDGPU_ASIC_ADDR_H

src/amd/addrlib/core/addrcommon.h

@@ -36,11 +36,17 @@
 
 #include "addrinterface.h"
 
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
+// ADDR_LNX_KERNEL_BUILD is for internal build
+// Moved from addrinterface.h so __KERNEL__ is not needed any more
+#if ADDR_LNX_KERNEL_BUILD // || (defined(__GNUC__) && defined(__KERNEL__))
+    #include "lnx_common_defs.h" // ported from cmmqs
+#elif !defined(__APPLE__) || defined(HAVE_TSERVER)
+    #include <assert.h>
+    #include <stdlib.h>
+    #include <string.h>
+#endif
 
-#if !defined(DEBUG)
+#if BRAHMA_BUILD && !defined(DEBUG)
 #ifdef NDEBUG
 #define DEBUG 0
 #else
@@ -73,7 +79,18 @@
     #define ADDR_ANALYSIS_ASSUME(expr) do { (void)(expr); } while (0)
 #endif
 
-#define ADDR_ASSERT(__e) assert(__e)
+#if BRAHMA_BUILD
+    #define ADDR_ASSERT(__e) assert(__e)
+#elif DEBUG
+    #define ADDR_ASSERT(__e)                                \
+        do {                                                    \
+            ADDR_ANALYSIS_ASSUME(__e);                          \
+            if ( !((__e) ? TRUE : FALSE)) { ADDR_DBG_BREAK(); } \
+        } while (0)
+#else //DEBUG
+    #define ADDR_ASSERT(__e) ADDR_ANALYSIS_ASSUME(__e)
+#endif //DEBUG
+
 #define ADDR_ASSERT_ALWAYS() ADDR_DBG_BREAK()
 #define ADDR_UNHANDLED_CASE() ADDR_ASSERT(!"Unhandled case")
 #define ADDR_NOT_IMPLEMENTED() ADDR_ASSERT(!"Not implemented");
@@ -154,8 +171,6 @@
 #endif // DEBUG
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 
-#define ADDR_C_ASSERT(__e) typedef char __ADDR_C_ASSERT__[(__e) ? 1 : -1]
-
 namespace Addr
 {
 

src/amd/addrlib/core/addrelemlib.cpp

@@ -1271,9 +1271,6 @@ VOID ElemLib::RestoreSurfaceInfo(
     UINT_32 height;
     UINT_32 bpp;
 
-    BOOL_32 bBCnFormat = FALSE;
-    (void)bBCnFormat;
-
     ADDR_ASSERT(pBpp != NULL);
     ADDR_ASSERT(pWidth != NULL && pHeight != NULL);
 
@@ -1292,17 +1289,22 @@ VOID ElemLib::RestoreSurfaceInfo(
             break;
         case ADDR_PACKED_GBGR:
         case ADDR_PACKED_BGRG:
-            originalBits = bpp; // 32-bit packed ==> 2 32-bit result
+            if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
+            {
+                originalBits = bpp / expandX;
+            }
+            else
+            {
+                originalBits = bpp; // 32-bit packed ==> 2 32-bit result
+            }
             break;
         case ADDR_PACKED_BC1: // Fall through
         case ADDR_PACKED_BC4:
             originalBits = 64;
-            bBCnFormat = TRUE;
             break;
         case ADDR_PACKED_BC2: // Fall through
         case ADDR_PACKED_BC3: // Fall through
         case ADDR_PACKED_BC5:
-            bBCnFormat = TRUE;
             // fall through
         case ADDR_PACKED_ASTC:
         case ADDR_PACKED_ETC2_128BPP:
@@ -1392,11 +1394,27 @@ UINT_32 ElemLib::GetBitsPerPixel(
             break;
         case ADDR_FMT_GB_GR: // treat as FMT_8_8
             elemMode = ADDR_PACKED_GBGR;
-            bpp     = 16;
+            if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
+            {
+                bpp     = 32;
+                expandX = 2;
+            }
+            else
+            {
+                bpp     = 16;
+            }
             break;
         case ADDR_FMT_BG_RG: // treat as FMT_8_8
             elemMode = ADDR_PACKED_BGRG;
-            bpp     = 16;
+            if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
+            {
+                bpp     = 32;
+                expandX = 2;
+            }
+            else
+            {
+                bpp     = 16;
+            }
             break;
         case ADDR_FMT_8_8_8_8:
         case ADDR_FMT_2_10_10_10:

src/amd/addrlib/core/addrlib.cpp

@@ -218,16 +218,7 @@ ADDR_E_RETURNCODE Lib::Create(
                 }
                 break;
             case CIASICIDGFXENGINE_ARCTICISLAND:
-                switch (pCreateIn->chipFamily)
-                {
-                    case FAMILY_AI:
-                    case FAMILY_RV:
-                        pLib = Gfx9HwlInit(&client);
-                        break;
-                    default:
-                        ADDR_ASSERT_ALWAYS();
-                        break;
-                }
+                pLib = Gfx9HwlInit(&client);
                 break;
             default:
                 ADDR_ASSERT_ALWAYS();

src/amd/addrlib/core/addrlib.h

@@ -38,7 +38,11 @@
 #include "addrobject.h"
 #include "addrelemlib.h"
 
-#include "amdgpu_asic_addr.h"
+#if BRAHMA_BUILD
+#include "amdgpu_id.h"
+#else
+#include "atiid.h"
+#endif
 
 #ifndef CIASICIDGFXENGINE_R600
 #define CIASICIDGFXENGINE_R600 0x00000006
@@ -122,123 +126,6 @@ enum BankSwapSize
     ADDR_BANKSWAP_1KB = 1024,
 };
 
-/**
-****************************************************************************************************
-* @brief Enums that define max compressed fragments config
-****************************************************************************************************
-*/
-enum NumMaxCompressedFragmentsConfig
-{
-    ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS   = 0x00000000,
-    ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS   = 0x00000001,
-    ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS   = 0x00000002,
-    ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS   = 0x00000003,
-};
-
-/**
-****************************************************************************************************
-* @brief Enums that define num pipes config
-****************************************************************************************************
-*/
-enum NumPipesConfig
-{
-    ADDR_CONFIG_1_PIPE                       = 0x00000000,
-    ADDR_CONFIG_2_PIPE                       = 0x00000001,
-    ADDR_CONFIG_4_PIPE                       = 0x00000002,
-    ADDR_CONFIG_8_PIPE                       = 0x00000003,
-    ADDR_CONFIG_16_PIPE                      = 0x00000004,
-    ADDR_CONFIG_32_PIPE                      = 0x00000005,
-    ADDR_CONFIG_64_PIPE                      = 0x00000006,
-};
-
-/**
-****************************************************************************************************
-* @brief Enums that define num banks config
-****************************************************************************************************
-*/
-enum NumBanksConfig
-{
-    ADDR_CONFIG_1_BANK                       = 0x00000000,
-    ADDR_CONFIG_2_BANK                       = 0x00000001,
-    ADDR_CONFIG_4_BANK                       = 0x00000002,
-    ADDR_CONFIG_8_BANK                       = 0x00000003,
-    ADDR_CONFIG_16_BANK                      = 0x00000004,
-};
-
-/**
-****************************************************************************************************
-* @brief Enums that define num rb per shader engine config
-****************************************************************************************************
-*/
-enum NumRbPerShaderEngineConfig
-{
-    ADDR_CONFIG_1_RB_PER_SHADER_ENGINE       = 0x00000000,
-    ADDR_CONFIG_2_RB_PER_SHADER_ENGINE       = 0x00000001,
-    ADDR_CONFIG_4_RB_PER_SHADER_ENGINE       = 0x00000002,
-};
-
-/**
-****************************************************************************************************
-* @brief Enums that define num shader engines config
-****************************************************************************************************
-*/
-enum NumShaderEnginesConfig
-{
-    ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
-    ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
-    ADDR_CONFIG_4_SHADER_ENGINE              = 0x00000002,
-    ADDR_CONFIG_8_SHADER_ENGINE              = 0x00000003,
-};
-
-/**
-****************************************************************************************************
-* @brief Enums that define pipe interleave size config
-****************************************************************************************************
-*/
-enum PipeInterleaveSizeConfig
-{
-    ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
-    ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
-    ADDR_CONFIG_PIPE_INTERLEAVE_1KB          = 0x00000002,
-    ADDR_CONFIG_PIPE_INTERLEAVE_2KB          = 0x00000003,
-};
-
-/**
-****************************************************************************************************
-* @brief Enums that define row size config
-****************************************************************************************************
-*/
-enum RowSizeConfig
-{
-    ADDR_CONFIG_1KB_ROW                      = 0x00000000,
-    ADDR_CONFIG_2KB_ROW                      = 0x00000001,
-    ADDR_CONFIG_4KB_ROW                      = 0x00000002,
-};
-
-/**
-****************************************************************************************************
-* @brief Enums that define bank interleave size config
-****************************************************************************************************
-*/
-enum BankInterleaveSizeConfig
-{
-    ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
-    ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
-    ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
-    ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
-};
-
-/**
-****************************************************************************************************
-* @brief Enums that define engine tile size config
-****************************************************************************************************
-*/
-enum ShaderEngineTileSizeConfig
-{
-    ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
-    ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
-};
-
 /**
 ****************************************************************************************************
 * @brief This class contains asic independent address lib functionalities

src/amd/addrlib/core/addrlib1.cpp

@@ -1281,54 +1281,36 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo(
 
         if (returnCode == ADDR_OK)
         {
-            if (pIn->flags.tcCompatible)
+            pOut->bpp = ComputeHtileInfo(pIn->flags,
+                                         pIn->pitch,
+                                         pIn->height,
+                                         pIn->numSlices,
+                                         pIn->isLinear,
+                                         isWidth8,
+                                         isHeight8,
+                                         pIn->pTileInfo,
+                                         &pOut->pitch,
+                                         &pOut->height,
+                                         &pOut->htileBytes,
+                                         &pOut->macroWidth,
+                                         &pOut->macroHeight,
+                                         &pOut->sliceSize,
+                                         &pOut->baseAlign);
+
+            if (pIn->flags.tcCompatible && (pIn->numSlices > 1))
             {
-                const UINT_32 sliceSize = pIn->pitch * pIn->height * 4 / (8 * 8);
-                const UINT_32 align     = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes;
+                pOut->sliceSize = pIn->pitch * pIn->height * 4 / (8 * 8);
 
-                if (pIn->numSlices > 1)
+                const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes;
+
+                if ((pOut->sliceSize % align) == 0)
                 {
-                    const UINT_32 surfBytes = (sliceSize * pIn->numSlices);
-
-                    pOut->sliceSize        = sliceSize;
-                    pOut->htileBytes       = pIn->flags.skipTcCompatSizeAlign ?
-                                             surfBytes : PowTwoAlign(surfBytes, align);
-                    pOut->sliceInterleaved = ((sliceSize % align) != 0) ? TRUE : FALSE;
+                    pOut->sliceInterleaved = FALSE;
                 }
                 else
                 {
-                    pOut->sliceSize        = pIn->flags.skipTcCompatSizeAlign ?
-                                             sliceSize : PowTwoAlign(sliceSize, align);
-                    pOut->htileBytes       = pOut->sliceSize;
-                    pOut->sliceInterleaved = FALSE;
+                    pOut->sliceInterleaved = TRUE;
                 }
-
-                pOut->nextMipLevelCompressible = ((sliceSize % align) == 0) ? TRUE : FALSE;
-
-                pOut->pitch       = pIn->pitch;
-                pOut->height      = pIn->height;
-                pOut->baseAlign   = align;
-                pOut->macroWidth  = 0;
-                pOut->macroHeight = 0;
-                pOut->bpp         = 32;
-            }
-            else
-            {
-                pOut->bpp = ComputeHtileInfo(pIn->flags,
-                                             pIn->pitch,
-                                             pIn->height,
-                                             pIn->numSlices,
-                                             pIn->isLinear,
-                                             isWidth8,
-                                             isHeight8,
-                                             pIn->pTileInfo,
-                                             &pOut->pitch,
-                                             &pOut->height,
-                                             &pOut->htileBytes,
-                                             &pOut->macroWidth,
-                                             &pOut->macroHeight,
-                                             &pOut->sliceSize,
-                                             &pOut->baseAlign);
             }
         }
     }
@@ -2180,8 +2162,6 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
 {
     UINT_32 pipe;
     UINT_32 numPipes;
-    UINT_32 numGroupBits;
-    (void)numGroupBits;
     UINT_32 numPipeBits;
     UINT_32 macroTilePitch;
     UINT_32 macroTileHeight;
@@ -2224,7 +2204,6 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
     //
     // Compute the number of group and pipe bits.
     //
-    numGroupBits = Log2(m_pipeInterleaveBytes);
     numPipeBits  = Log2(numPipes);
 
     UINT_32 groupBits = 8 * m_pipeInterleaveBytes;
@@ -3525,10 +3504,6 @@ VOID Lib::ComputeMipLevel(
     ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
     ) const
 {
-    // Check if HWL has handled
-    BOOL_32 hwlHandled = FALSE;
-    (void)hwlHandled;
-
     if (ElemLib::IsBlockCompressed(pIn->format))
     {
         if (pIn->mipLevel == 0)
@@ -3542,7 +3517,7 @@ VOID Lib::ComputeMipLevel(
         }
     }
 
-    hwlHandled = HwlComputeMipLevel(pIn);
+    HwlComputeMipLevel(pIn);
 }
 
 /**

src/amd/addrlib/core/addrlib2.cpp

@@ -355,11 +355,6 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoord(
         {
             returnCode = ComputeSurfaceAddrFromCoordTiled(&localIn, pOut);
         }
-
-        if (returnCode == ADDR_OK)
-        {
-            pOut->prtBlockIndex = static_cast<UINT_32>(pOut->addr / (64 * 1024));
-        }
     }
 
     return returnCode;
@@ -465,7 +460,8 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo(
 */
 ADDR_E_RETURNCODE Lib::ComputeHtileAddrFromCoord(
     const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*   pIn,    ///< [in] input structure
-    ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*        pOut)   ///< [out] output structure
+    ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*        pOut    ///< [out] output structure
+    ) const
 {
     ADDR_E_RETURNCODE returnCode;
 
@@ -496,7 +492,8 @@ ADDR_E_RETURNCODE Lib::ComputeHtileAddrFromCoord(
 */
 ADDR_E_RETURNCODE Lib::ComputeHtileCoordFromAddr(
     const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT*   pIn,    ///< [in] input structure
-    ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*        pOut)   ///< [out] output structure
+    ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*        pOut    ///< [out] output structure
+    ) const
 {
     ADDR_E_RETURNCODE returnCode;
 
@@ -563,7 +560,8 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskInfo(
 */
 ADDR_E_RETURNCODE Lib::ComputeCmaskAddrFromCoord(
     const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*   pIn,    ///< [in] input structure
-    ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut)   ///< [out] output structure
+    ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut    ///< [out] output structure
+    ) const
 {
     ADDR_E_RETURNCODE returnCode;
 
@@ -782,7 +780,8 @@ ADDR_E_RETURNCODE Lib::ComputeDccInfo(
 */
 ADDR_E_RETURNCODE Lib::ComputeDccAddrFromCoord(
     const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,    ///< [in] input structure
-    ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*      pOut)   ///< [out] output structure
+    ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*      pOut    ///< [out] output structure
+    ) const
 {
     ADDR_E_RETURNCODE returnCode;
 
@@ -1048,7 +1047,77 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfoLinear(
      ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut    ///< [out] output structure
      ) const
 {
-    return HwlComputeSurfaceInfoLinear(pIn, pOut);
+    ADDR_E_RETURNCODE returnCode = ADDR_OK;
+
+    UINT_32 pitch = 0;
+    UINT_32 actualHeight = 0;
+    UINT_32 elementBytes = pIn->bpp >> 3;
+    const UINT_32 alignment = pIn->flags.prt ? PrtAlignment : 256;
+
+    if (IsTex1d(pIn->resourceType))
+    {
+        if (pIn->height > 1)
+        {
+            returnCode = ADDR_INVALIDPARAMS;
+        }
+        else
+        {
+            const UINT_32 pitchAlignInElement = alignment / elementBytes;
+            pitch = PowTwoAlign(pIn->width, pitchAlignInElement);
+            actualHeight = pIn->numMipLevels;
+
+            if (pIn->flags.prt == FALSE)
+            {
+                returnCode = ApplyCustomizedPitchHeight(pIn, elementBytes, pitchAlignInElement,
+                                                        &pitch, &actualHeight);
+            }
+
+            if (returnCode == ADDR_OK)
+            {
+                if (pOut->pMipInfo != NULL)
+                {
+                    for (UINT_32 i = 0; i < pIn->numMipLevels; i++)
+                    {
+                        pOut->pMipInfo[i].offset = pitch * elementBytes * i;
+                        pOut->pMipInfo[i].pitch = pitch;
+                        pOut->pMipInfo[i].height = 1;
+                        pOut->pMipInfo[i].depth = 1;
+                    }
+                }
+            }
+        }
+    }
+    else
+    {
+        returnCode = ComputeSurfaceLinearPadding(pIn, &pitch, &actualHeight, pOut->pMipInfo);
+    }
+
+    if ((pitch == 0) || (actualHeight == 0))
+    {
+        returnCode = ADDR_INVALIDPARAMS;
+    }
+
+    if (returnCode == ADDR_OK)
+    {
+        pOut->pitch = pitch;
+        pOut->height = pIn->height;
+        pOut->numSlices = pIn->numSlices;
+        pOut->mipChainPitch = pitch;
+        pOut->mipChainHeight = actualHeight;
+        pOut->mipChainSlice = pOut->numSlices;
+        pOut->epitchIsHeight = (pIn->numMipLevels > 1) ? TRUE : FALSE;
+        pOut->sliceSize = static_cast<UINT_64>(pOut->pitch) * actualHeight * elementBytes;
+        pOut->surfSize = pOut->sliceSize * pOut->numSlices;
+        pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? (pIn->bpp / 8) : alignment;
+        pOut->blockWidth = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? 1 : (256 * 8 / pIn->bpp);
+        pOut->blockHeight = 1;
+        pOut->blockSlices = 1;
+    }
+
+    // Post calculation validate
+    ADDR_ASSERT(pOut->sliceSize > 0);
+
+    return returnCode;
 }
 
 /**
@@ -1101,8 +1170,6 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoordLinear(
     {
         ADDR2_COMPUTE_SURFACE_INFO_INPUT  localIn  = {0};
         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT localOut = {0};
-        ADDR2_MIP_INFO                    mipInfo[MaxMipLevels];
-
         localIn.bpp          = pIn->bpp;
         localIn.flags        = pIn->flags;
         localIn.width        = Max(pIn->unalignedWidth, 1u);
@@ -1110,21 +1177,32 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoordLinear(
         localIn.numSlices    = Max(pIn->numSlices, 1u);
         localIn.numMipLevels = Max(pIn->numMipLevels, 1u);
         localIn.resourceType = pIn->resourceType;
-
         if (localIn.numMipLevels <= 1)
         {
             localIn.pitchInElement = pIn->pitchInElement;
         }
-
-        localOut.pMipInfo = mipInfo;
-
         returnCode = ComputeSurfaceInfoLinear(&localIn, &localOut);
 
         if (returnCode == ADDR_OK)
         {
-            pOut->addr        = (localOut.sliceSize * pIn->slice) +
-                                mipInfo[pIn->mipId].offset +
-                                (pIn->y * mipInfo[pIn->mipId].pitch + pIn->x) * (pIn->bpp >> 3);
+            UINT_32 elementBytes = pIn->bpp >> 3;
+            UINT_64 sliceOffsetInSurf = localOut.sliceSize * pIn->slice;
+            UINT_64 mipOffsetInSlice = 0;
+            UINT_64 offsetInMip = 0;
+
+            if (IsTex1d(pIn->resourceType))
+            {
+                offsetInMip = static_cast<UINT_64>(pIn->x) * elementBytes;
+                mipOffsetInSlice = static_cast<UINT_64>(pIn->mipId) * localOut.pitch * elementBytes;
+            }
+            else
+            {
+                UINT_64 mipStartHeight = SumGeo(localIn.height, pIn->mipId);
+                mipOffsetInSlice = static_cast<UINT_64>(mipStartHeight) * localOut.pitch * elementBytes;
+                offsetInMip = (pIn->y * localOut.pitch + pIn->x) * elementBytes;
+            }
+
+            pOut->addr = sliceOffsetInSurf + mipOffsetInSlice + offsetInMip;
             pOut->bitPosition = 0;
         }
         else
@@ -1320,6 +1398,73 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceCoordFromAddrTiled(
     return returnCode;
 }
 
+/**
+************************************************************************************************************************
+*   Lib::ComputeSurfaceInfoLinear
+*
+*   @brief
+*       Internal function to calculate padding for linear swizzle 2D/3D surface
+*
+*   @return
+*       N/A
+************************************************************************************************************************
+*/
+ADDR_E_RETURNCODE Lib::ComputeSurfaceLinearPadding(
+    const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,    ///< [in] input srtucture
+    UINT_32* pMipmap0PaddedWidth,                   ///< [out] padded width in element
+    UINT_32* pSlice0PaddedHeight,                   ///< [out] padded height for HW
+    ADDR2_MIP_INFO* pMipInfo                        ///< [out] per mip information
+    ) const
+{
+    ADDR_E_RETURNCODE returnCode = ADDR_OK;
+
+    UINT_32 elementBytes = pIn->bpp >> 3;
+    UINT_32 pitchAlignInElement = 0;
+
+    if (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL)
+    {
+        ADDR_ASSERT(pIn->numMipLevels <= 1);
+        ADDR_ASSERT(pIn->numSlices <= 1);
+        pitchAlignInElement = 1;
+    }
+    else
+    {
+        pitchAlignInElement = (256 / elementBytes);
+    }
+
+    UINT_32 mipChainWidth = PowTwoAlign(pIn->width, pitchAlignInElement);
+    UINT_32 slice0PaddedHeight = pIn->height;
+
+    returnCode = ApplyCustomizedPitchHeight(pIn, elementBytes, pitchAlignInElement,
+                                            &mipChainWidth, &slice0PaddedHeight);
+
+    if (returnCode == ADDR_OK)
+    {
+        UINT_32 mipChainHeight = 0;
+        UINT_32 mipHeight = pIn->height;
+
+        for (UINT_32 i = 0; i < pIn->numMipLevels; i++)
+        {
+            if (pMipInfo != NULL)
+            {
+                pMipInfo[i].offset = mipChainWidth * mipChainHeight * elementBytes;
+                pMipInfo[i].pitch = mipChainWidth;
+                pMipInfo[i].height = mipHeight;
+                pMipInfo[i].depth = 1;
+            }
+
+            mipChainHeight += mipHeight;
+            mipHeight = RoundHalf(mipHeight);
+            mipHeight = Max(mipHeight, 1u);
+        }
+
+        *pMipmap0PaddedWidth = mipChainWidth;
+        *pSlice0PaddedHeight = (pIn->numMipLevels > 1) ? mipChainHeight : slice0PaddedHeight;
+    }
+
+    return returnCode;
+}
+
 /**
 ************************************************************************************************************************
 *   Lib::ComputeBlockDimensionForSurf

src/amd/addrlib/core/addrlib2.h

@@ -103,63 +103,63 @@ public:
     // For data surface
     ADDR_E_RETURNCODE ComputeSurfaceInfo(
         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
-        ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
+        ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
 
     ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const;
+        ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
 
     ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
-        const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
-        ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut) const;
+        const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT*  pIn,
+        ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
 
     // For HTile
     ADDR_E_RETURNCODE ComputeHtileInfo(
         const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
-        ADDR2_COMPUTE_HTILE_INFO_OUTPUT*      pOut) const;
+        ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
 
     ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
-        const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
 
     ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
-        const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
-        ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT*  pIn,
+        ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
 
     // For CMask
     ADDR_E_RETURNCODE ComputeCmaskInfo(
         const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
-        ADDR2_COMPUTE_CMASK_INFO_OUTPUT*      pOut) const;
+        ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
 
     ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
-        const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
 
     ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
-        const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
-        ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*      pOut) const;
+        const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT*  pIn,
+        ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
 
     // For FMask
     ADDR_E_RETURNCODE ComputeFmaskInfo(
-        const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
-        ADDR2_COMPUTE_FMASK_INFO_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_FMASK_INFO_INPUT*  pIn,
+        ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
 
     ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
-        const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*      pOut) const;
+        const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
 
     ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
-        const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
-        ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*      pOut) const;
+        const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT*  pIn,
+        ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
 
     // For DCC key
     ADDR_E_RETURNCODE ComputeDccInfo(
         const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
-        ADDR2_COMPUTE_DCCINFO_OUTPUT*      pOut) const;
+        ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
 
     ADDR_E_RETURNCODE ComputeDccAddrFromCoord(
-        const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const;
 
     // Misc
     ADDR_E_RETURNCODE ComputePipeBankXor(
@@ -197,8 +197,6 @@ protected:
     static const UINT_32 PrtAlignment = 64 * 1024;
     static const UINT_32 MaxMacroBits = 20;
 
-    static const UINT_32 MaxMipLevels = 16;
-
     // Checking block size
     BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const
     {
@@ -404,32 +402,32 @@ protected:
     }
 
     virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
-        const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*      pOut)
+        const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const
     {
         ADDR_NOT_IMPLEMENTED();
         return ADDR_NOTSUPPORTED;
     }
 
     virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
-        const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*      pOut)
+        const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const
     {
         ADDR_NOT_IMPLEMENTED();
         return ADDR_NOTSUPPORTED;
     }
 
     virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
-        const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*      pOut)
+        const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const
     {
         ADDR_NOT_IMPLEMENTED();
         return ADDR_NOTSUPPORTED;
     }
 
     virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
-        const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
-        ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*      pOut)
+        const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT*  pIn,
+        ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const
     {
         ADDR_NOT_IMPLEMENTED();
         return ADDR_NOTSUPPORTED;
@@ -534,14 +532,6 @@ protected:
         return ADDR_NOTIMPLEMENTED;
     }
 
-    virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
-         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
-         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const
-    {
-        ADDR_NOT_IMPLEMENTED();
-        return ADDR_NOTIMPLEMENTED;
-    }
-
     virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const
@@ -575,6 +565,12 @@ protected:
         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
 
+    ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
+        const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
+        UINT_32* pMipmap0PaddedWidth,
+        UINT_32* pSlice0PaddedHeight,
+        ADDR2_MIP_INFO* pMipInfo = NULL) const;
+
     ADDR_E_RETURNCODE ComputeSurfaceInfoTiled(
         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
@@ -761,10 +757,10 @@ protected:
 
     ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
-        UINT_32                                 elementBytes,
-        UINT_32                                 pitchAlignInElement,
-        UINT_32*                                pPitch,
-        UINT_32*                                pHeight) const;
+        UINT_32  elementBytes,
+        UINT_32  pitchAlignInElement,
+        UINT_32* pPitch,
+        UINT_32* pHeight) const;
 
     VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
 

src/amd/addrlib/gfx9/coord.cpp

@@ -34,20 +34,20 @@ Coordinate::Coordinate()
     ord = 0;
 }
 
-Coordinate::Coordinate(INT_8 c, INT_32 n)
+Coordinate::Coordinate(INT_8 c, UINT_32 n)
 {
-    set(c, n);
+    set(c,n);
 }
 
-VOID Coordinate::set(INT_8 c, INT_32 n)
+VOID Coordinate::set(INT_8 c, UINT_32 n)
 {
     dim = c;
     ord = static_cast<INT_8>(n);
 }
 
-UINT_32 Coordinate::ison(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m) const
+UINT_32 Coordinate::ison(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m)
 {
-    UINT_32 bit = static_cast<UINT_32>(1ull << static_cast<UINT_32>(ord));
+    UINT_32 bit = 1 << (UINT_32)ord;
     UINT_32 out = 0;
 
     switch (dim)
@@ -234,7 +234,7 @@ UINT_32 CoordTerm::getsize()
     return num_coords;
 }
 
-UINT_32 CoordTerm::getxor(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m) const
+UINT_32 CoordTerm::getxor(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m)
 {
     UINT_32 out = 0;
     for (UINT_32 i = 0; i < num_coords; i++)
@@ -386,7 +386,7 @@ UINT_32 CoordEq::getsize()
     return m_numBits;
 }
 
-UINT_64 CoordEq::solve(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m) const
+UINT_64 CoordEq::solve(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m)
 {
     UINT_64 out = 0;
     for (UINT_32 i = 0; i < m_numBits; i++)
@@ -401,7 +401,7 @@ UINT_64 CoordEq::solve(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s, UINT_32 m) co
 
 VOID CoordEq::solveAddr(
     UINT_64 addr, UINT_32 sliceInM,
-    UINT_32& x, UINT_32& y, UINT_32& z, UINT_32& s, UINT_32& m) const
+    UINT_32& x, UINT_32& y, UINT_32& z, UINT_32& s, UINT_32& m)
 {
     UINT_32 xBitsValid = 0;
     UINT_32 yBitsValid = 0;

src/amd/addrlib/gfx9/coord.h

@@ -33,12 +33,12 @@ class Coordinate
 {
 public:
     Coordinate();
-    Coordinate(INT_8 c, INT_32 n);
+    Coordinate(INT_8 c, UINT_32 n);
 
-    VOID set(INT_8 c, INT_32 n);
-    UINT_32 ison(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0) const;
-    INT_8   getdim();
-    INT_8   getord();
+    VOID set(INT_8 c, UINT_32 n);
+    UINT_32 ison(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0);
+    INT_8 getdim();
+    INT_8 getord();
 
     BOOL_32 operator==(const Coordinate& b);
     BOOL_32 operator<(const Coordinate& b);
@@ -64,7 +64,7 @@ public:
     BOOL_32 Exists(Coordinate& co);
     VOID copyto(CoordTerm& cl);
     UINT_32 getsize();
-    UINT_32 getxor(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0) const;
+    UINT_32 getxor(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0);
 
     VOID getsmallest(Coordinate& co);
     UINT_32 Filter(INT_8 f, Coordinate& co, UINT_32 start = 0, INT_8 axis = '\0');
@@ -87,9 +87,9 @@ public:
     BOOL_32 Exists(Coordinate& co);
     VOID resize(UINT_32 n);
     UINT_32 getsize();
-    virtual UINT_64 solve(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0) const;
+    virtual UINT_64 solve(UINT_32 x, UINT_32 y, UINT_32 z = 0, UINT_32 s = 0, UINT_32 m = 0);
     virtual VOID solveAddr(UINT_64 addr, UINT_32 sliceInM,
-                           UINT_32& x, UINT_32& y, UINT_32& z, UINT_32& s, UINT_32& m) const;
+                           UINT_32& x, UINT_32& y, UINT_32& z, UINT_32& s, UINT_32& m);
 
     VOID copy(CoordEq& o, UINT_32 start = 0, UINT_32 num = 0xFFFFFFFF);
     VOID reverse(UINT_32 start = 0, UINT_32 num = 0xFFFFFFFF);

src/amd/addrlib/gfx9/gfx9addrlib.h

@@ -65,9 +65,7 @@ struct Gfx9ChipSettings
         // Misc configuration bits
         UINT_32 metaBaseAlignFix    : 1;
         UINT_32 depthPipeXorDisable : 1;
-        UINT_32 htileAlignFix       : 1;
-        UINT_32 applyAliasFix       : 1;
-        UINT_32 reserved2           : 28;
+        UINT_32 reserved2           : 30;
     };
 };
 
@@ -83,28 +81,6 @@ enum Gfx9DataType
     Gfx9DataFmask
 };
 
-/**
-************************************************************************************************************************
-* @brief GFX9 meta equation parameters
-************************************************************************************************************************
-*/
-struct MetaEqParams
-{
-    UINT_32          maxMip;
-    UINT_32          elementBytesLog2;
-    UINT_32          numSamplesLog2;
-    ADDR2_META_FLAGS metaFlag;
-    Gfx9DataType     dataSurfaceType;
-    AddrSwizzleMode  swizzleMode;
-    AddrResourceType resourceType;
-    UINT_32          metaBlkWidthLog2;
-    UINT_32          metaBlkHeightLog2;
-    UINT_32          metaBlkDepthLog2;
-    UINT_32          compBlkWidthLog2;
-    UINT_32          compBlkHeightLog2;
-    UINT_32          compBlkDepthLog2;
-};
-
 /**
 ************************************************************************************************************************
 * @brief This class is the GFX9 specific address library
@@ -163,31 +139,31 @@ protected:
 
     virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
         const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
-        ADDR2_COMPUTE_HTILE_INFO_OUTPUT*      pOut) const;
+        ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
 
     virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
         const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
-        ADDR2_COMPUTE_CMASK_INFO_OUTPUT*      pOut) const;
+        ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
 
     virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
         const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
-        ADDR2_COMPUTE_DCCINFO_OUTPUT*      pOut) const;
+        ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
 
     virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
-        const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
 
     virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
-        const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
 
     virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
-        const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
-        ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT*  pIn,
+        ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
 
     virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
-        const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
-        ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*      pOut);
+        const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT*  pIn,
+        ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const;
 
     virtual UINT_32 HwlGetEquationIndex(
         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
@@ -230,7 +206,17 @@ protected:
 
         if (IsXor(swizzleMode))
         {
-            baseAlign = GetBlockSize(swizzleMode);
+            if (m_settings.isVega10 || m_settings.isRaven)
+            {
+                baseAlign = GetBlockSize(swizzleMode);
+            }
+            else
+            {
+                UINT_32 blockSizeLog2 = GetBlockSizeLog2(swizzleMode);
+                UINT_32 pipeBits = GetPipeXorBits(blockSizeLog2);
+                UINT_32 bankBits = GetBankXorBits(blockSizeLog2);
+                baseAlign = 1 << (Min(blockSizeLog2, m_pipeInterleaveLog2 + pipeBits+ bankBits));
+            }
         }
         else
         {
@@ -263,10 +249,6 @@ protected:
          const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
          ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
 
-    virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
-         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
-         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
-
     virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const;
@@ -370,10 +352,6 @@ protected:
         return compressBlkDim;
     }
 
-
-    static const UINT_32          MaxSeLog2      = 3;
-    static const UINT_32          MaxRbPerSeLog2 = 2;
-
     static const Dim3d            Block256_3dS[MaxNumOfBpp];
     static const Dim3d            Block256_3dZ[MaxNumOfBpp];
 
@@ -397,8 +375,6 @@ protected:
     // Equation lookup table according to bpp and tile index
     UINT_32                 m_equationLookupTable[MaxRsrcType][MaxSwMode][MaxElementBytesLog2];
 
-    static const UINT_32    MaxCachedMetaEq = 2;
-
 private:
     virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(
         ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
@@ -406,7 +382,7 @@ private:
     virtual BOOL_32 HwlInitGlobalParams(
         const ADDR_CREATE_INPUT* pCreateIn);
 
-    VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const;
+    static VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2);
 
     VOID GetDataEquation(CoordEq* pDataEq, Gfx9DataType dataSurfaceType,
                          AddrSwizzleMode swizzleMode, AddrResourceType resourceType,
@@ -417,7 +393,7 @@ private:
                          UINT_32 numSamplesLog2, Gfx9DataType dataSurfaceType,
                          AddrSwizzleMode swizzleMode, AddrResourceType resourceType) const;
 
-    VOID GenMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip,
+    VOID GetMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip,
                          UINT_32 elementBytesLog2, UINT_32 numSamplesLog2,
                          ADDR2_META_FLAGS metaFlag, Gfx9DataType dataSurfaceType,
                          AddrSwizzleMode swizzleMode, AddrResourceType resourceType,
@@ -425,8 +401,6 @@ private:
                          UINT_32 metaBlkDepthLog2, UINT_32 compBlkWidthLog2,
                          UINT_32 compBlkHeightLog2, UINT_32 compBlkDepthLog2) const;
 
-    const CoordEq* GetMetaEquation(const MetaEqParams& metaEqParams);
-
     virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
 
     VOID GetMetaMipInfo(UINT_32 numMipLevels, Dim3d* pMetaBlkDim,
@@ -434,17 +408,7 @@ private:
                         UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
                         UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
 
-    ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
-        const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
-        UINT_32*                                pMipmap0PaddedWidth,
-        UINT_32*                                pSlice0PaddedHeight,
-        ADDR2_MIP_INFO*                         pMipInfo = NULL) const;
-
     Gfx9ChipSettings m_settings;
-
-    CoordEq      m_cachedMetaEq[MaxCachedMetaEq];
-    MetaEqParams m_cachedMetaEqKey[MaxCachedMetaEq];
-    UINT_32      m_metaEqOverrideIndex;
 };
 
 } // V2

src/amd/addrlib/gfx9/rbmap.h

@@ -0,0 +1,142 @@
+/*
+ * Copyright © 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+
+// This class RB_MAP contains the top-level calculation functions which are used to generate rb id map based rb id equations
+
+#ifndef __RB_MAP_H
+#define __RB_MAP_H
+
+#include "coord.h"
+
+class RB_MAP
+{
+public:
+
+    enum MAX_VALUES {
+        MAX_SES_LOG2 = 3,
+        MAX_RBS_LOG2 = 2
+    };
+
+    enum COMPRESSED_DATABLOCKS_IN_METABLOCK_PER_RB_LOG2 {
+        COMPRESSED_DATABLOCKS_IN_METABLOCK_PER_RB_LOG2_2D = 10,
+        COMPRESSED_DATABLOCKS_IN_METABLOCK_PER_RB_LOG2_3D = 18
+    };
+
+    RB_MAP(void);
+
+    void Get_Comp_Block_Screen_Space( CoordEq& addr, int bytes_log2, int* w, int* h, int* d = NULL);
+
+    void Get_Meta_Block_Screen_Space( int num_comp_blocks_log2, bool is_thick, bool y_biased,
+                                      int comp_block_width_log2, int comp_block_height_log2, int comp_block_depth_log2,
+                                      int& meta_block_width_log2, int& meta_block_height_log2, int& meta_block_depth_log2 );
+    void cap_pipe( int xmode, bool is_thick, int& num_ses_log2, int bpp_log2, int num_samples_log2, int pipe_interleave_log2,
+                   int& block_size_log2, int& num_pipes_log2 );
+
+    void Get_Data_Offset_Equation( CoordEq& data_eq, int data_type, int bpp_log2, int num_samples_log2, int block_size_log2 );
+
+    void Get_RB_Equation( CoordEq& rb_equation, int num_ses_log2, int num_rbs_log2 );
+
+    void Get_Pipe_Equation( CoordEq& pipe_equation, CoordEq& addr,
+                           int pipe_interleave_log2,
+                           int num_pipes_log2,
+                           int block_size_log2,
+                           int num_samples_log2,
+                           int xmode, int data_type
+                         );
+
+    void get_meta_miptail_coord( int& x, int& y, int& z, int mip_in_tail, int blk_width_log2, int blk_height_log2, int blk_depth_log2 );
+
+    void get_mip_coord( int& x, int& y, int& z, int mip,
+                        int meta_blk_width_log2, int meta_blk_height_log2, int meta_blk_depth_log2,
+                        int data_blk_width_log2, int data_blk_height_log2,
+                        int& surf_width, int& surf_height, int& surf_depth, int epitch, int max_mip,
+                        int data_type, int bpp_log2, bool meta_linear );
+
+    void get_mip_coord_linear( int& x, int& y, int& z, int mip, int data_blk_width_log2, int data_blk_height_log2,
+                               int& surf_width, int& surf_height, int& surf_depth, int epitch, int max_mip, int data_type, int bpp_log2 );
+
+    void get_mip_coord_nonlinear( int& x, int& y, int& z, int mip, int meta_blk_width_log2, int meta_blk_height_log2, int meta_blk_depth_log2,
+                                  int& surf_width, int& surf_height, int& surf_depth, int epitch, int max_mip, int data_type );
+
+    void get_meta_eq( CoordEq& metaaddr, int max_mip, int num_ses_log2, int num_rbs_log2, int &num_pipes_log2,
+                      int block_size_log2, int bpp_log2, int num_samples_log2, int max_comp_frag_log2,
+                      int pipe_interleave_log2, int xmode, int data_type, int meta_alignment, bool meta_linear);
+
+#if 0
+    long get_meta_addr( int x, int y, int z, int s, int mip,
+                        int surf_width, int surf_height, int surf_depth, int epitch,
+                        long surf_base, int pipe_xor, int max_mip,
+                        int num_ses_log2, int num_rbs_log2, int num_pipes_log2,
+                        int block_size_log2, int bpp_log2, int num_samples_log2, int max_comp_frag_log2,
+                        int pipe_interleave_log2, int xmode, int data_type, int meta_alignment, bool meta_linear);
+#endif
+
+    long get_meta_addr_calc( int x, int y, int z, int s,
+                    long surf_base, int element_bytes_log2, int num_samples_log2, int max_comp_frag_log2,
+                    long pitch, long slice,
+                    int max_mip,
+                    //int swizzle_mode,
+                    int xmode, int pipe_xor, int block_size_log2,
+                    /*int num_banks_log2,*/ int num_pipes_log2,
+                    int pipe_interleave_log2, int meta_alignment, int dim_type, int x_mip_org, int y_mip_org,
+                    int z_mip_org, int num_ses_log2, int num_rbs_log2, /*bool se_affinity_enable,*/ int data_type,
+                    int l2_metablk_w, int l2_metablk_h, int l2_metablk_d, bool meta_linear);
+
+    void Initialize(void);
+
+public:
+    enum XOR_RANGE {
+        NONE = 0,
+        XOR = 1,
+        PRT = 2
+    };
+
+
+    enum DATA_TYPE_ENUM {
+        DATA_COLOR1D,
+        DATA_COLOR2D,
+        DATA_COLOR3D_S,
+        DATA_COLOR3D_Z,
+        DATA_Z_STENCIL,
+        DATA_FMASK,
+        DATA_COLOR2D_LINEAR,
+        DATA_COLOR3D_D_NOT_USED  // should not be used; use COLOR2D instead
+    };
+
+    enum META_ALIGNMENT {
+        META_ALIGN_NONE,
+        META_ALIGN_PIPE,
+        META_ALIGN_RB,
+        META_ALIGN_PIPE_RB
+    };
+
+    CoordEq   rb_equation[MAX_SES_LOG2+1][MAX_RBS_LOG2+1];
+    CoordEq   zaddr [4][4];
+    CoordEq   caddr [5][4];
+    CoordEq   c3addr[5][2];
+};
+
+#endif

src/amd/addrlib/inc/chip/gfx9/gfx9_gb_reg.h

@@ -27,14 +27,6 @@
  * of the Software.
  */
 
-#include "util/u_endian.h"
-
-#if defined(PIPE_ARCH_LITTLE_ENDIAN)
-#define LITTLEENDIAN_CPU
-#elif defined(PIPE_ARCH_BIG_ENDIAN)
-#define BIGENDIAN_CPU
-#endif
-
 //
 // Make sure the necessary endian defines are there.
 //

src/amd/addrlib/inc/chip/r800/si_gb_reg.h

@@ -27,14 +27,6 @@
  * of the Software.
  */
 
-#include "util/u_endian.h"
-
-#if defined(PIPE_ARCH_LITTLE_ENDIAN)
-#define LITTLEENDIAN_CPU
-#elif defined(PIPE_ARCH_BIG_ENDIAN)
-#define BIGENDIAN_CPU
-#endif
-
 //
 // Make sure the necessary endian defines are there.
 //

src/amd/addrlib/inc/lnx_common_defs.h

@@ -0,0 +1,129 @@
+/*
+ * Copyright © 2014 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+#ifndef _lnx_common_defs_h_
+#define _lnx_common_defs_h_
+
+#if DBG
+#include <stdarg.h>                         // We do not have any choice: need variable
+                                            // number of parameters support for debug
+                                            // build.
+#endif                                      // #if DBG
+
+//
+// --------------  External functions from Linux kernel driver ----------------
+//
+// Note: The definitions/declararions below must match the original ones.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef unsigned long __ke_size_t;              // as it is defined in firegl_public.h
+typedef int           __kernel_ptrdiff_t;       // as it is defined in posix_types.h
+
+
+#if !defined(ATI_API_CALL)
+#define ATI_API_CALL __attribute__((regparm(0)))
+#endif
+
+extern void * ATI_API_CALL __ke_memset(void* s, int c, __ke_size_t count);
+extern void * ATI_API_CALL __ke_memcpy(void* d, const void* s, __ke_size_t count);
+extern ATI_API_CALL __ke_size_t __ke_strlen(const char *s);
+extern char* ATI_API_CALL __ke_strcpy(char* d, const char* s);
+extern char* ATI_API_CALL __ke_strncpy(char* d, const char* s, __ke_size_t count);
+extern void __ke_printk(const char* fmt, ...);
+
+extern int ATI_API_CALL __ke_snprintf(char* buf, __ke_size_t size, const char* fmt, ...);
+extern int ATI_API_CALL KCL_CopyFromUserSpace(void* to, const void* from, __ke_size_t size);
+extern int ATI_API_CALL KCL_CopyToUserSpace(void* to, const void* from, __ke_size_t size);
+#define __ke_copy_from_user  KCL_CopyFromUserSpace
+#define __ke_copy_to_user    KCL_CopyToUserSpace
+extern int ATI_API_CALL __ke_verify_area(int type, const void * addr, unsigned long size);
+
+extern unsigned long ATI_API_CALL KAS_GetTickCounter(void);
+extern unsigned long ATI_API_CALL KAS_GetTicksPerSecond(void);
+
+
+#if DBG
+extern int ATI_API_CALL __ke_vsnprintf(char *buf, __ke_size_t size, const char *fmt, va_list ap);
+#define vsnprintf(_dst, _size, _fmt, varg)  __ke_snprintf(_dst, _size, _fmt, varg)
+#endif                                      // #if DBG
+
+
+// Note: This function is not defined in firegl_public.h.
+void    firegl_hardwareHangRecovery(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+//
+// --------------------------  C/C++ standard typedefs ----------------------------
+//
+#ifdef __SIZE_TYPE__
+typedef __SIZE_TYPE__       size_t;
+#else                                       // #ifdef __SIZE_TYPE__
+typedef unsigned int        size_t;
+#endif                                      // #ifdef __SIZE_TYPE__
+
+#ifdef __PTRDIFF_TYPE__
+typedef __PTRDIFF_TYPE__    ptrdiff_t;
+#else                                       // #ifdef __PTRDIFF_TYPE__
+typedef int                 ptrdiff_t;
+#endif                                      // #ifdef __PTRDIFF_TYPE__
+
+#ifndef NULL
+#ifdef __cplusplus
+#define NULL    __null
+#else
+#define NULL    ((void *)0)
+#endif
+#endif
+
+
+//
+// -------------------------  C/C++ standard macros ---------------------------
+//
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)  // as it is defined in stddef.h
+#define CHAR_BIT            8                                   // as it is defined in limits.h
+
+//
+// ---------------------------------  C RTL -----------------------------------
+//
+
+#define memset(_p, _v, _n)                  __ke_memset(_p, _v, _n)
+#define memcpy(_d, _s, _n)                  __ke_memcpy(_d, _s, _n)
+#define strlen(_s)                          __ke_strlen(_s)
+#define strcpy(_d, _s)                      __ke_strcpy(_d, _s)
+#define strncpy(_d, _s, _n)                 __ke_strncpy(_d, _s, _n)
+// Note: C99 supports macros with variable number of arguments. GCC also supports this C99 feature as
+//       C++ extension.
+#define snprintf(_dst, _size, _fmt, arg...) __ke_snprintf(_dst, _size, _fmt, ##arg)
+
+
+#endif                                      // #ifdef _lnx_common_defs_h_
+

src/amd/addrlib/meson.build

@@ -38,9 +38,11 @@ files_addrlib = files(
   'gfx9/coord.h',
   'gfx9/gfx9addrlib.cpp',
   'gfx9/gfx9addrlib.h',
-  'amdgpu_asic_addr.h',
+  'gfx9/rbmap.cpp',
+  'gfx9/rbmap.h',
   'inc/chip/gfx9/gfx9_gb_reg.h',
   'inc/chip/r800/si_gb_reg.h',
+  'inc/lnx_common_defs.h',
   'r800/chip/si_ci_vi_merged_enum.h',
   'r800/ciaddrlib.cpp',
   'r800/ciaddrlib.h',
@@ -53,11 +55,9 @@ files_addrlib = files(
 libamdgpu_addrlib = static_library(
   'addrlib',
   files_addrlib,
-  include_directories : [
-    include_directories(
-      'core', 'inc/chip/gfx9', 'inc/chip/r800', 'gfx9/chip', 'r800/chip',
-    ),
-    inc_amd_common, inc_src,
-  ],
-  cpp_args : cpp_vis_args,
+  include_directories : include_directories(
+    'core', 'inc/chip/gfx9', 'inc/chip/r800', 'gfx9/chip', 'r800/chip',
+    '../common', '../../'),
+  cpp_args : [cpp_vis_args, '-DBRAHMA_BUILD=1'],
+  build_by_default : false,
 )

src/amd/addrlib/r800/ciaddrlib.cpp

@@ -35,7 +35,15 @@
 
 #include "si_gb_reg.h"
 
-#include "amdgpu_asic_addr.h"
+#include "si_ci_vi_merged_enum.h"
+
+#if BRAHMA_BUILD
+#include "amdgpu_id.h"
+#else
+#include "ci_id.h"
+#include "kv_id.h"
+#include "vi_id.h"
+#endif
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -180,6 +188,7 @@ CiLib::CiLib(const Client* pClient)
     m_allowNonDispThickModes(FALSE)
 {
     m_class = CI_ADDRLIB;
+    memset(&m_settings, 0, sizeof(m_settings));
 }
 
 /**
@@ -441,6 +450,7 @@ BOOL_32 CiLib::HwlInitGlobalParams(
     // read the correct pipes from tile mode table
     if (m_settings.isHawaii)
     {
+        // Hawaii has 16-pipe, see GFXIP_Config_Summary.xls
         m_pipes = 16;
     }
     else if (m_settings.isBonaire || m_settings.isSpectre)
@@ -590,9 +600,9 @@ INT_32 CiLib::HwlPostCheckTileIndex(
 ****************************************************************************************************
 */
 ADDR_E_RETURNCODE CiLib::HwlSetupTileCfg(
-    UINT_32         bpp,            ///< Bits per pixel
-    INT_32          index,          ///< Tile index
-    INT_32          macroModeIndex, ///< Index in macro tile mode table(CI)
+    UINT_32         bpp,            ///< [in] Bits per pixel
+    INT_32          index,          ///< [in] Tile index
+    INT_32          macroModeIndex, ///< [in] Index in macro tile mode table(CI)
     ADDR_TILEINFO*  pInfo,          ///< [out] Tile Info
     AddrTileMode*   pMode,          ///< [out] Tile mode
     AddrTileType*   pType           ///< [out] Tile type
@@ -701,12 +711,13 @@ ADDR_E_RETURNCODE CiLib::HwlComputeSurfaceInfo(
 
     ADDR_E_RETURNCODE retCode = SiLib::HwlComputeSurfaceInfo(pIn, pOut);
 
+
     if ((pIn->mipLevel > 0) &&
         (pOut->tcCompatible == TRUE) &&
         (pOut->tileMode != pIn->tileMode) &&
         (m_settings.isVolcanicIslands == TRUE))
     {
-        pOut->tcCompatible = CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileType, pOut);
+        CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileType, pOut);
     }
 
     if (pOut->macroModeIndex == TileIndexNoMacroIndex)
@@ -1561,7 +1572,7 @@ VOID CiLib::HwlSetupTileInfo(
 
     if (flags.tcCompatible)
     {
-        flags.tcCompatible = CheckTcCompatibility(pTileInfo, bpp, tileMode, inTileType, pOut);
+        CheckTcCompatibility(pTileInfo, bpp, tileMode, inTileType, pOut);
     }
 
     pOut->tcCompatible = flags.tcCompatible;
@@ -2260,21 +2271,19 @@ BOOL_32 CiLib::DepthStencilTileCfgMatch(
 *   CiLib::DepthStencilTileCfgMatch
 *
 *   @brief
-*       Check if tc compatibility is available
+*       Turn off TcCompatible if requirement is not met
 *   @return
-*       If tc compatibility is not available
+*       N/A
 ****************************************************************************************************
 */
-BOOL_32 CiLib::CheckTcCompatibility(
-    const ADDR_TILEINFO*                    pTileInfo,    ///< [in] input tile info
-    UINT_32                                 bpp,          ///< [in] Bits per pixel
-    AddrTileMode                            tileMode,     ///< [in] input tile mode
-    AddrTileType                            tileType,     ///< [in] input tile type
-    const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut          ///< [in] output surf info
+VOID CiLib::CheckTcCompatibility(
+    const ADDR_TILEINFO*              pTileInfo,    ///< [in] input tile info
+    UINT_32                           bpp,          ///< [in] Bits per pixel
+    AddrTileMode                      tileMode,     ///< [in] input tile mode
+    AddrTileType                      tileType,     ///< [in] input tile type
+    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut          ///< [out] out structure
     ) const
 {
-    BOOL_32 tcCompatible = TRUE;
-
     if (IsMacroTiled(tileMode))
     {
         if (tileType != ADDR_DEPTH_SAMPLE_ORDER)
@@ -2300,7 +2309,7 @@ BOOL_32 CiLib::CheckTcCompatibility(
 
                 if (m_rowSize < colorTileSplit)
                 {
-                    tcCompatible = FALSE;
+                    pOut->tcCompatible = FALSE;
                 }
             }
         }
@@ -2308,10 +2317,8 @@ BOOL_32 CiLib::CheckTcCompatibility(
     else
     {
         // Client should not enable tc compatible for linear and 1D tile modes.
-        tcCompatible = FALSE;
+        pOut->tcCompatible = FALSE;
     }
-
-    return tcCompatible;
 }
 
 } // V1

src/amd/addrlib/r800/ciaddrlib.h

@@ -42,6 +42,37 @@ namespace Addr
 namespace V1
 {
 
+/**
+****************************************************************************************************
+* @brief CI specific settings structure.
+****************************************************************************************************
+*/
+struct CIChipSettings
+{
+    struct
+    {
+        UINT_32 isSeaIsland : 1;
+        UINT_32 isBonaire   : 1;
+        UINT_32 isKaveri    : 1;
+        UINT_32 isSpectre   : 1;
+        UINT_32 isSpooky    : 1;
+        UINT_32 isKalindi   : 1;
+        // Hawaii is GFXIP 7.2
+        UINT_32 isHawaii    : 1;
+
+        // VI
+        UINT_32 isVolcanicIslands : 1;
+        UINT_32 isIceland         : 1;
+        UINT_32 isTonga           : 1;
+        UINT_32 isFiji            : 1;
+        UINT_32 isPolaris10       : 1;
+        UINT_32 isPolaris11       : 1;
+        UINT_32 isPolaris12       : 1;
+        // VI fusion (Carrizo)
+        UINT_32 isCarrizo         : 1;
+    };
+};
+
 /**
 ****************************************************************************************************
 * @brief This class is the CI specific address library
@@ -177,8 +208,9 @@ private:
         const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,
         ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut) const;
 
-    BOOL_32 CheckTcCompatibility(const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
-                                 AddrTileType tileType, const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
+    VOID CheckTcCompatibility(
+        const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
+         AddrTileType tileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
 
     static const UINT_32    MacroTileTableSize = 16;
     static const UINT_32    PrtMacroModeOffset = MacroTileTableSize / 2;
@@ -189,6 +221,8 @@ private:
     ADDR_TILEINFO           m_macroTileTable[MacroTileTableSize];
     UINT_32                 m_noOfMacroEntries;
     BOOL_32                 m_allowNonDispThickModes;
+
+    CIChipSettings          m_settings;
 };
 
 } // V1

src/amd/addrlib/r800/egbaddrlib.cpp

@@ -739,12 +739,13 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMicroTiled(
 
     AdjustPitchAlignment(flags, pPitchAlign);
 
-    // Workaround 2 for 1D tiling -  There is HW bug for Carrizo,
+    // ECR#393489
+    // Workaround 2 for 1D tiling -  There is HW bug for Carrizo
     // where it requires the following alignments for 1D tiling.
     if (flags.czDispCompatible && (mipLevel == 0))
     {
         *pBaseAlign  = PowTwoAlign(*pBaseAlign, 4096);                         //Base address MOD 4096 = 0
-        *pPitchAlign = PowTwoAlign(*pPitchAlign, 512 / (BITS_TO_BYTES(bpp)));  //(8 lines * pitch * bytes per pixel) MOD 4096 = 0
+        *pPitchAlign = PowTwoAlign(*pPitchAlign, 512 / (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0
     }
     // end Carrizo workaround for 1D tilling
 
@@ -1090,8 +1091,6 @@ AddrTileMode EgBasedLib::ComputeSurfaceMipLevelTileMode(
     ADDR_TILEINFO*      pTileInfo       ///< [in] ptr to bank structure
     ) const
 {
-    UINT_64 bytesPerSlice;
-    (void)bytesPerSlice;
     UINT_32 bytesPerTile;
 
     AddrTileMode expTileMode = baseTileMode;
@@ -1101,7 +1100,6 @@ AddrTileMode EgBasedLib::ComputeSurfaceMipLevelTileMode(
     //
     // Compute the size of a slice.
     //
-    bytesPerSlice = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
     bytesPerTile = BITS_TO_BYTES(MicroTilePixels * microTileThickness * NextPow2(bpp) * numSamples);
 
     //
@@ -1331,6 +1329,12 @@ UINT_64 EgBasedLib::DispatchComputeSurfaceAddrFromCoord(
     UINT_32*            pBitPosition       = &pOut->bitPosition;
     UINT_64             addr;
 
+#if ADDR_AM_BUILD
+    UINT_32             addr5Bit           = 0;
+    UINT_32             addr5Swizzle       = pIn->addr5Swizzle;
+    BOOL_32             is32ByteTile       = pIn->is32ByteTile;
+#endif
+
     // ADDR_DEPTH_SAMPLE_ORDER = non-disp + depth-sample-order
     if (microTileType == ADDR_DEPTH_SAMPLE_ORDER)
     {
@@ -1435,6 +1439,23 @@ UINT_64 EgBasedLib::DispatchComputeSurfaceAddrFromCoord(
             break;
     }
 
+#if ADDR_AM_BUILD
+    if (m_chipFamily >= ADDR_CHIP_FAMILY_NI)
+    {
+        if (addr5Swizzle && isDepthSampleOrder && is32ByteTile)
+        {
+            UINT_32 tx = x >> 3;
+            UINT_32 ty = y >> 3;
+            UINT_32 tileBits = ((ty&0x3) << 2) | (tx&0x3);
+
+            tileBits = tileBits & addr5Swizzle;
+            addr5Bit = XorReduce(tileBits, 4);
+
+            addr = addr | static_cast<UINT_64>(addr5Bit << 5);
+        }
+    }
+#endif
+
     return addr;
 }
 
@@ -2730,8 +2751,6 @@ ADDR_E_RETURNCODE EgBasedLib::HwlComputeBaseSwizzle(
         { 0, 7, 14, 5, 12, 3, 10, 1, 8, 15, 6, 13, 4, 11, 2, 9 }, // ADDR_SURF_16_BANK
     };
 
-    UINT_32 pipes = HwlGetPipes(pTileInfo);
-    (void)pipes;
     UINT_32 banks = pTileInfo ? pTileInfo->banks : 2;
     UINT_32 hwNumBanks;
 
@@ -3360,6 +3379,20 @@ ADDR_E_RETURNCODE EgBasedLib::HwlComputeFmaskAddrFromCoord(
 {
     ADDR_E_RETURNCODE retCode = ADDR_OK;
 
+#if ADDR_AM_BUILD
+    if ((pIn->x > pIn->pitch)               ||
+        (pIn->y > pIn->height)              ||
+        (pIn->numSamples > m_maxSamples)    ||
+        (pIn->sample >= m_maxSamples))
+    {
+        retCode = ADDR_INVALIDPARAMS;
+    }
+    else
+    {
+        pOut->addr = DispatchComputeFmaskAddrFromCoord(pIn, pOut);
+    }
+#endif
+
     return retCode;
 }
 
@@ -3379,9 +3412,618 @@ ADDR_E_RETURNCODE EgBasedLib::HwlComputeFmaskCoordFromAddr(
 {
     ADDR_E_RETURNCODE retCode = ADDR_OK;
 
+#if ADDR_AM_BUILD
+    if ((pIn->bitPosition >= 8) ||
+        (pIn->numSamples > m_maxSamples))
+    {
+        retCode = ADDR_INVALIDPARAMS;
+    }
+    else
+    {
+        DispatchComputeFmaskCoordFromAddr(pIn, pOut);
+    }
+#endif
+
     return retCode;
 }
 
+#if ADDR_AM_BUILD
+/**
+****************************************************************************************************
+*   EgBasedLib::DispatchComputeFmaskAddrFromCoord
+*
+*   @brief
+*       Computes the FMASK address and bit position from a coordinate.
+*   @return
+*       The byte address
+****************************************************************************************************
+*/
+UINT_64 EgBasedLib::DispatchComputeFmaskAddrFromCoord(
+    const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*   pIn,    ///< [in] input structure
+    ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*        pOut    ///< [out] output structure
+    ) const
+{
+    UINT_32             x                 = pIn->x;
+    UINT_32             y                 = pIn->y;
+    UINT_32             slice             = pIn->slice;
+    UINT_32             sample            = pIn->sample;
+    UINT_32             plane             = pIn->plane;
+    UINT_32             pitch             = pIn->pitch;
+    UINT_32             height            = pIn->height;
+    UINT_32             numSamples        = pIn->numSamples;
+    AddrTileMode        tileMode          = pIn->tileMode;
+    BOOL_32             ignoreSE          = pIn->ignoreSE;
+    ADDR_TILEINFO*      pTileInfo         = pIn->pTileInfo;
+    BOOL_32             resolved          = pIn->resolved;
+
+    UINT_32* pBitPosition = &pOut->bitPosition;
+    UINT_64 addr          = 0;
+
+    ADDR_ASSERT(numSamples > 1);
+    ADDR_ASSERT(Thickness(tileMode) == 1);
+
+    switch (tileMode)
+    {
+        case ADDR_TM_1D_TILED_THIN1:
+            addr = ComputeFmaskAddrFromCoordMicroTiled(x,
+                                                       y,
+                                                       slice,
+                                                       sample,
+                                                       plane,
+                                                       pitch,
+                                                       height,
+                                                       numSamples,
+                                                       tileMode,
+                                                       resolved,
+                                                       pBitPosition);
+            break;
+        case ADDR_TM_2D_TILED_THIN1: //fall through
+        case ADDR_TM_3D_TILED_THIN1:
+            UINT_32 pipeSwizzle;
+            UINT_32 bankSwizzle;
+
+            if (m_configFlags.useCombinedSwizzle)
+            {
+                ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
+                                       &bankSwizzle, &pipeSwizzle);
+            }
+            else
+            {
+                pipeSwizzle = pIn->pipeSwizzle;
+                bankSwizzle = pIn->bankSwizzle;
+            }
+
+            addr = ComputeFmaskAddrFromCoordMacroTiled(x,
+                                                       y,
+                                                       slice,
+                                                       sample,
+                                                       plane,
+                                                       pitch,
+                                                       height,
+                                                       numSamples,
+                                                       tileMode,
+                                                       pipeSwizzle,
+                                                       bankSwizzle,
+                                                       ignoreSE,
+                                                       pTileInfo,
+                                                       resolved,
+                                                       pBitPosition);
+            break;
+        default:
+            *pBitPosition = 0;
+            break;
+    }
+
+    return addr;
+}
+
+/**
+****************************************************************************************************
+*   EgBasedLib::ComputeFmaskAddrFromCoordMicroTiled
+*
+*   @brief
+*       Computes the FMASK address and bit position from a coordinate for 1D tilied (micro
+*       tiled)
+*   @return
+*       The byte address
+****************************************************************************************************
+*/
+UINT_64 EgBasedLib::ComputeFmaskAddrFromCoordMicroTiled(
+    UINT_32             x,              ///< [in] x coordinate
+    UINT_32             y,              ///< [in] y coordinate
+    UINT_32             slice,          ///< [in] slice index
+    UINT_32             sample,         ///< [in] sample number
+    UINT_32             plane,          ///< [in] plane number
+    UINT_32             pitch,          ///< [in] surface pitch in pixels
+    UINT_32             height,         ///< [in] surface height in pixels
+    UINT_32             numSamples,     ///< [in] number of samples
+    AddrTileMode        tileMode,       ///< [in] tile mode
+    BOOL_32             resolved,       ///< [in] TRUE if this is for resolved fmask
+    UINT_32*            pBitPosition    ///< [out] pointer to returned bit position
+    ) const
+{
+    UINT_64 addr = 0;
+    UINT_32 effectiveBpp;
+    UINT_32 effectiveSamples;
+
+    //
+    // 2xAA use the same layout as 4xAA
+    //
+    if (numSamples == 2)
+    {
+        numSamples = 4;
+    }
+
+    //
+    // Compute the number of planes.
+    //
+    if (resolved == FALSE)
+    {
+        effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
+        effectiveBpp = numSamples;
+
+        //
+        // Compute the address just like a color surface with numSamples bits per element and
+        // numPlanes samples.
+        //
+        addr = ComputeSurfaceAddrFromCoordMicroTiled(x,
+                                                     y,
+                                                     slice,
+                                                     plane, // sample
+                                                     effectiveBpp,
+                                                     pitch,
+                                                     height,
+                                                     effectiveSamples,
+                                                     tileMode,
+                                                     ADDR_NON_DISPLAYABLE,
+                                                     FALSE,
+                                                     pBitPosition);
+
+        //
+        // Compute the real bit position. Each (sample, plane) is stored with one bit per sample.
+        //
+
+        //
+        // Compute the pixel index with in the micro tile
+        //
+        UINT_32 pixelIndex = ComputePixelIndexWithinMicroTile(x % 8,
+                                                              y % 8,
+                                                              slice,
+                                                              1,
+                                                              tileMode,
+                                                              ADDR_NON_DISPLAYABLE);
+
+        *pBitPosition = ((pixelIndex * numSamples) + sample) & (BITS_PER_BYTE-1);
+
+        UINT_64 bitAddr = BYTES_TO_BITS(addr) + *pBitPosition;
+
+        addr = bitAddr / 8;
+    }
+    else
+    {
+        effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
+        effectiveSamples = 1;
+
+        //
+        // Compute the address just like a color surface with numSamples bits per element and
+        // numPlanes samples.
+        //
+        addr = ComputeSurfaceAddrFromCoordMicroTiled(x,
+                                                     y,
+                                                     slice,
+                                                     sample,
+                                                     effectiveBpp,
+                                                     pitch,
+                                                     height,
+                                                     effectiveSamples,
+                                                     tileMode,
+                                                     ADDR_NON_DISPLAYABLE,
+                                                     TRUE,
+                                                     pBitPosition);
+    }
+
+    return addr;
+}
+
+/**
+****************************************************************************************************
+*   EgBasedLib::ComputeFmaskAddrFromCoordMacroTiled
+*
+*   @brief
+*       Computes the FMASK address and bit position from a coordinate for 2D tilied (macro
+*       tiled)
+*   @return
+*       The byte address
+****************************************************************************************************
+*/
+UINT_64 EgBasedLib::ComputeFmaskAddrFromCoordMacroTiled(
+    UINT_32             x,              ///< [in] x coordinate
+    UINT_32             y,              ///< [in] y coordinate
+    UINT_32             slice,          ///< [in] slice index
+    UINT_32             sample,         ///< [in] sample number
+    UINT_32             plane,          ///< [in] plane number
+    UINT_32             pitch,          ///< [in] surface pitch in pixels
+    UINT_32             height,         ///< [in] surface height in pixels
+    UINT_32             numSamples,     ///< [in] number of samples
+    AddrTileMode        tileMode,       ///< [in] tile mode
+    UINT_32             pipeSwizzle,    ///< [in] pipe swizzle
+    UINT_32             bankSwizzle,    ///< [in] bank swizzle
+    BOOL_32             ignoreSE,       ///< [in] TRUE if ignore shader engine
+    ADDR_TILEINFO*      pTileInfo,      ///< [in] bank structure.**All fields to be valid on entry**
+    BOOL_32             resolved,       ///< [in] TRUE if this is for resolved fmask
+    UINT_32*            pBitPosition    ///< [out] pointer to returned bit position
+    ) const
+{
+    UINT_64 addr = 0;
+    UINT_32 effectiveBpp;
+    UINT_32 effectiveSamples;
+
+    //
+    // 2xAA use the same layout as 4xAA
+    //
+    if (numSamples == 2)
+    {
+        numSamples = 4;
+    }
+
+    //
+    // Compute the number of planes.
+    //
+    if (resolved == FALSE)
+    {
+        effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
+        effectiveBpp = numSamples;
+
+        //
+        // Compute the address just like a color surface with numSamples bits per element and
+        // numPlanes samples.
+        //
+        addr = ComputeSurfaceAddrFromCoordMacroTiled(x,
+                                                     y,
+                                                     slice,
+                                                     plane, // sample
+                                                     effectiveBpp,
+                                                     pitch,
+                                                     height,
+                                                     effectiveSamples,
+                                                     tileMode,
+                                                     ADDR_NON_DISPLAYABLE,// isdisp
+                                                     ignoreSE,// ignore_shader
+                                                     FALSE,// depth_sample_order
+                                                     pipeSwizzle,
+                                                     bankSwizzle,
+                                                     pTileInfo,
+                                                     pBitPosition);
+
+        //
+        // Compute the real bit position. Each (sample, plane) is stored with one bit per sample.
+        //
+
+
+        //
+        // Compute the pixel index with in the micro tile
+        //
+        UINT_32 pixelIndex = ComputePixelIndexWithinMicroTile(x ,
+                                                              y ,
+                                                              slice,
+                                                              effectiveBpp,
+                                                              tileMode,
+                                                              ADDR_NON_DISPLAYABLE);
+
+        *pBitPosition = ((pixelIndex * numSamples) + sample) & (BITS_PER_BYTE-1);
+
+        UINT_64 bitAddr = BYTES_TO_BITS(addr) + *pBitPosition;
+
+        addr = bitAddr / 8;
+
+    }
+    else
+    {
+        effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
+        effectiveSamples = 1;
+
+        //
+        // Compute the address just like a color surface with numSamples bits per element and
+        // numPlanes samples.
+        //
+        addr = ComputeSurfaceAddrFromCoordMacroTiled(x,
+                                                     y,
+                                                     slice,
+                                                     sample,
+                                                     effectiveBpp,
+                                                     pitch,
+                                                     height,
+                                                     effectiveSamples,
+                                                     tileMode,
+                                                     ADDR_NON_DISPLAYABLE,
+                                                     ignoreSE,
+                                                     TRUE,
+                                                     pipeSwizzle,
+                                                     bankSwizzle,
+                                                     pTileInfo,
+                                                     pBitPosition);
+    }
+
+    return addr;
+}
+
+/**
+****************************************************************************************************
+*   EgBasedLib::ComputeFmaskCoordFromAddrMicroTiled
+*
+*   @brief
+*       Compute (x,y,slice,sample,plane) coordinates from fmask address
+*   @return
+*       N/A
+*
+****************************************************************************************************
+*/
+VOID EgBasedLib::ComputeFmaskCoordFromAddrMicroTiled(
+    UINT_64             addr,       ///< [in] byte address
+    UINT_32             bitPosition,///< [in] bit position
+    UINT_32             pitch,      ///< [in] pitch in pixels
+    UINT_32             height,     ///< [in] height in pixels
+    UINT_32             numSamples, ///< [in] number of samples (of color buffer)
+    AddrTileMode        tileMode,   ///< [in] tile mode
+    BOOL_32             resolved,   ///< [in] TRUE if it is resolved fmask
+    UINT_32*            pX,         ///< [out] X coord
+    UINT_32*            pY,         ///< [out] Y coord
+    UINT_32*            pSlice,     ///< [out] slice index
+    UINT_32*            pSample,    ///< [out] sample index
+    UINT_32*            pPlane      ///< [out] plane index
+    ) const
+{
+    UINT_32 effectiveBpp;
+    UINT_32 effectiveSamples;
+
+    // 2xAA use the same layout as 4xAA
+    if (numSamples == 2)
+    {
+        numSamples = 4;
+    }
+
+    if (resolved == FALSE)
+    {
+        effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
+        effectiveBpp  = numSamples;
+
+        ComputeSurfaceCoordFromAddrMicroTiled(addr,
+                                              bitPosition,
+                                              effectiveBpp,
+                                              pitch,
+                                              height,
+                                              effectiveSamples,
+                                              tileMode,
+                                              0, // tileBase
+                                              0, // compBits
+                                              pX,
+                                              pY,
+                                              pSlice,
+                                              pPlane,
+                                              ADDR_NON_DISPLAYABLE, // microTileType
+                                              FALSE  // isDepthSampleOrder
+                                              );
+
+
+        if ( pSample )
+        {
+            *pSample = bitPosition % numSamples;
+        }
+    }
+    else
+    {
+        effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
+        effectiveSamples = 1;
+
+        ComputeSurfaceCoordFromAddrMicroTiled(addr,
+                                              bitPosition,
+                                              effectiveBpp,
+                                              pitch,
+                                              height,
+                                              effectiveSamples,
+                                              tileMode,
+                                              0,     // tileBase
+                                              0,     // compBits
+                                              pX,
+                                              pY,
+                                              pSlice,
+                                              pSample,
+                                              ADDR_NON_DISPLAYABLE, // microTileType
+                                              TRUE   // isDepthSampleOrder
+                                              );
+    }
+}
+
+/**
+****************************************************************************************************
+*   EgBasedLib::ComputeFmaskCoordFromAddrMacroTiled
+*
+*   @brief
+*       Compute (x,y,slice,sample,plane) coordinates from
+*       fmask address
+*   @return
+*       N/A
+*
+****************************************************************************************************
+*/
+VOID EgBasedLib::ComputeFmaskCoordFromAddrMacroTiled(
+    UINT_64             addr,       ///< [in] byte address
+    UINT_32             bitPosition,///< [in] bit position
+    UINT_32             pitch,      ///< [in] pitch in pixels
+    UINT_32             height,     ///< [in] height in pixels
+    UINT_32             numSamples, ///< [in] number of samples (of color buffer)
+    AddrTileMode        tileMode,   ///< [in] tile mode
+    UINT_32             pipeSwizzle,///< [in] pipe swizzle
+    UINT_32             bankSwizzle,///< [in] bank swizzle
+    BOOL_32             ignoreSE,   ///< [in] TRUE if ignore shader engine
+    ADDR_TILEINFO*      pTileInfo,  ///< [in] bank structure. **All fields to be valid on entry**
+    BOOL_32             resolved,   ///< [in] TRUE if it is resolved fmask
+    UINT_32*            pX,         ///< [out] X coord
+    UINT_32*            pY,         ///< [out] Y coord
+    UINT_32*            pSlice,     ///< [out] slice index
+    UINT_32*            pSample,    ///< [out] sample index
+    UINT_32*            pPlane      ///< [out] plane index
+    ) const
+{
+    UINT_32 effectiveBpp;
+    UINT_32 effectiveSamples;
+
+    // 2xAA use the same layout as 4xAA
+    if (numSamples == 2)
+    {
+        numSamples = 4;
+    }
+
+    //
+    // Compute the number of planes.
+    //
+    if (resolved == FALSE)
+    {
+        effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
+        effectiveBpp  = numSamples;
+
+        ComputeSurfaceCoordFromAddrMacroTiled(addr,
+                                              bitPosition,
+                                              effectiveBpp,
+                                              pitch,
+                                              height,
+                                              effectiveSamples,
+                                              tileMode,
+                                              0, // No tileBase
+                                              0, // No compBits
+                                              ADDR_NON_DISPLAYABLE,
+                                              ignoreSE,
+                                              FALSE,
+                                              pipeSwizzle,
+                                              bankSwizzle,
+                                              pTileInfo,
+                                              pX,
+                                              pY,
+                                              pSlice,
+                                              pPlane);
+
+        if (pSample)
+        {
+            *pSample = bitPosition % numSamples;
+        }
+    }
+    else
+    {
+        effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
+        effectiveSamples = 1;
+
+        ComputeSurfaceCoordFromAddrMacroTiled(addr,
+                                              bitPosition,
+                                              effectiveBpp,
+                                              pitch,
+                                              height,
+                                              effectiveSamples,
+                                              tileMode,
+                                              0, // No tileBase
+                                              0, // No compBits
+                                              ADDR_NON_DISPLAYABLE,
+                                              ignoreSE,
+                                              TRUE,
+                                              pipeSwizzle,
+                                              bankSwizzle,
+                                              pTileInfo,
+                                              pX,
+                                              pY,
+                                              pSlice,
+                                              pSample);
+    }
+}
+
+/**
+****************************************************************************************************
+*   EgBasedLib::DispatchComputeFmaskCoordFromAddr
+*
+*   @brief
+*       Compute (x,y,slice,sample,plane) coordinates from
+*       fmask address
+*   @return
+*       N/A
+*
+****************************************************************************************************
+*/
+VOID EgBasedLib::DispatchComputeFmaskCoordFromAddr(
+    const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*   pIn,    ///< [in] input structure
+    ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*        pOut    ///< [out] output structure
+    ) const
+{
+    UINT_64             addr              = pIn->addr;
+    UINT_32             bitPosition       = pIn->bitPosition;
+    UINT_32             pitch             = pIn->pitch;
+    UINT_32             height            = pIn->height;
+    UINT_32             numSamples        = pIn->numSamples;
+    AddrTileMode        tileMode          = pIn->tileMode;
+    BOOL_32             ignoreSE          = pIn->ignoreSE;
+    ADDR_TILEINFO*      pTileInfo         = pIn->pTileInfo;
+    BOOL_32             resolved          = pIn->resolved;
+
+    UINT_32*            pX      = &pOut->x;
+    UINT_32*            pY      = &pOut->y;
+    UINT_32*            pSlice  = &pOut->slice;
+    UINT_32*            pSample = &pOut->sample;
+    UINT_32*            pPlane  = &pOut->plane;
+
+    switch (tileMode)
+    {
+        case ADDR_TM_1D_TILED_THIN1:
+            ComputeFmaskCoordFromAddrMicroTiled(addr,
+                                                bitPosition,
+                                                pitch,
+                                                height,
+                                                numSamples,
+                                                tileMode,
+                                                resolved,
+                                                pX,
+                                                pY,
+                                                pSlice,
+                                                pSample,
+                                                pPlane);
+            break;
+        case ADDR_TM_2D_TILED_THIN1://fall through
+        case ADDR_TM_3D_TILED_THIN1:
+            UINT_32 pipeSwizzle;
+            UINT_32 bankSwizzle;
+
+            if (m_configFlags.useCombinedSwizzle)
+            {
+                ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
+                                       &bankSwizzle, &pipeSwizzle);
+            }
+            else
+            {
+                pipeSwizzle = pIn->pipeSwizzle;
+                bankSwizzle = pIn->bankSwizzle;
+            }
+
+            ComputeFmaskCoordFromAddrMacroTiled(addr,
+                                                bitPosition,
+                                                pitch,
+                                                height,
+                                                numSamples,
+                                                tileMode,
+                                                pipeSwizzle,
+                                                bankSwizzle,
+                                                ignoreSE,
+                                                pTileInfo,
+                                                resolved,
+                                                pX,
+                                                pY,
+                                                pSlice,
+                                                pSample,
+                                                pPlane);
+            break;
+        default:
+            ADDR_ASSERT_ALWAYS();
+            break;
+
+    }
+}
+#endif
+
 /**
 ****************************************************************************************************
 *   EgBasedLib::ComputeFmaskNumPlanesFromNumSamples

src/amd/addrlib/r800/siaddrlib.cpp

@@ -32,9 +32,16 @@
 */
 
 #include "siaddrlib.h"
+
 #include "si_gb_reg.h"
 
-#include "amdgpu_asic_addr.h"
+#include "si_ci_vi_merged_enum.h"
+
+#if BRAHMA_BUILD
+#include "amdgpu_id.h"
+#else
+#include "si_id.h"
+#endif
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2657,8 +2664,7 @@ ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
 
         if ((pIn->numSlices > 1) &&
             (IsMacroTiled(pOut->tileMode) == TRUE) &&
-            ((m_chipFamily == ADDR_CHIP_FAMILY_SI) ||
-             (IsPrtTileMode(pOut->tileMode) == FALSE)))
+            (m_chipFamily == ADDR_CHIP_FAMILY_SI))
         {
             pOut->equationIndex = ADDR_INVALID_EQUATION_INDEX;
         }
@@ -2816,8 +2822,8 @@ VOID SiLib::HwlCheckLastMacroTiledLvl(
 ****************************************************************************************************
 */
 AddrTileMode SiLib::HwlDegradeThickTileMode(
-    AddrTileMode        baseTileMode,   ///< base tile mode
-    UINT_32             numSlices,      ///< current number of slices
+    AddrTileMode        baseTileMode,   ///< [in] base tile mode
+    UINT_32             numSlices,      ///< [in] current number of slices
     UINT_32*            pBytesPerTile   ///< [in,out] pointer to bytes per slice
     ) const
 {
@@ -2957,9 +2963,9 @@ INT_32 SiLib::HwlPostCheckTileIndex(
 ****************************************************************************************************
 */
 ADDR_E_RETURNCODE SiLib::HwlSetupTileCfg(
-    UINT_32         bpp,            ///< Bits per pixel
-    INT_32          index,          ///< Tile index
-    INT_32          macroModeIndex, ///< Index in macro tile mode table(CI)
+    UINT_32         bpp,            ///< [in] Bits per pixel
+    INT_32          index,          ///< [in] Tile index
+    INT_32          macroModeIndex, ///< [in] Index in macro tile mode table(CI)
     ADDR_TILEINFO*  pInfo,          ///< [out] Tile Info
     AddrTileMode*   pMode,          ///< [out] Tile mode
     AddrTileType*   pType           ///< [out] Tile type

src/amd/addrlib/r800/siaddrlib.h

@@ -59,36 +59,18 @@ struct TileConfig
 * @brief SI specific settings structure.
 ****************************************************************************************************
 */
-struct SiChipSettings
+struct SIChipSettings
 {
-    UINT_32 isSouthernIsland  : 1;
-    UINT_32 isTahiti          : 1;
-    UINT_32 isPitCairn        : 1;
-    UINT_32 isCapeVerde       : 1;
-    // Oland/Hainan are of GFXIP 6.0, similar with SI
-    UINT_32 isOland           : 1;
-    UINT_32 isHainan          : 1;
-
-    // CI
-    UINT_32 isSeaIsland       : 1;
-    UINT_32 isBonaire         : 1;
-    UINT_32 isKaveri          : 1;
-    UINT_32 isSpectre         : 1;
-    UINT_32 isSpooky          : 1;
-    UINT_32 isKalindi         : 1;
-    // Hawaii is GFXIP 7.2
-    UINT_32 isHawaii          : 1;
-
-    // VI
-    UINT_32 isVolcanicIslands : 1;
-    UINT_32 isIceland         : 1;
-    UINT_32 isTonga           : 1;
-    UINT_32 isFiji            : 1;
-    UINT_32 isPolaris10       : 1;
-    UINT_32 isPolaris11       : 1;
-    UINT_32 isPolaris12       : 1;
-    // VI fusion
-    UINT_32 isCarrizo         : 1;
+    struct
+    {
+        UINT_32 isSouthernIsland    : 1;
+        UINT_32 isTahiti            : 1;
+        UINT_32 isPitCairn          : 1;
+        UINT_32 isCapeVerde         : 1;
+        /// Oland/Hainan are of GFXIP 6.0, similar with SI
+        UINT_32 isOland             : 1;
+        UINT_32 isHainan            : 1;
+    };
 };
 
 /**
@@ -330,12 +312,12 @@ protected:
 
     UINT_32                 m_uncompressDepthEqIndex;
 
-    SiChipSettings          m_settings;
-
 private:
 
     VOID ReadGbTileMode(UINT_32 regValue, TileConfig* pCfg) const;
     BOOL_32 InitTileSettingTable(const UINT_32 *pSetting, UINT_32 noOfEntries);
+
+    SIChipSettings          m_settings;
 };
 
 } // V1

src/amd/common/ac_binary.c

@@ -19,6 +19,10 @@
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
+ *
+ * Authors: Tom Stellard <thomas.stellard@amd.com>
+ *
+ * Based on radeon_elf_util.c.
  */
 
 #include "ac_binary.h"
@@ -298,16 +302,3 @@ void ac_shader_binary_read_config(struct ac_shader_binary *binary,
 	        conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(wavesize) * 256 * 4;
 	}
 }
-
-void ac_shader_binary_clean(struct ac_shader_binary *b)
-{
-	if (!b)
-		return;
-	FREE(b->code);
-	FREE(b->config);
-	FREE(b->rodata);
-	FREE(b->global_symbol_offsets);
-	FREE(b->relocs);
-	FREE(b->disasm_string);
-	FREE(b->llvm_ir_string);
-}

src/amd/common/ac_binary.h

@@ -19,6 +19,9 @@
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
+ *
+ * Authors: Tom Stellard <thomas.stellard@amd.com>
+ *
  */
 
 #ifndef AC_BINARY_H
@@ -96,6 +99,5 @@ void ac_shader_binary_read_config(struct ac_shader_binary *binary,
 				  struct ac_shader_config *conf,
 				  unsigned symbol_offset,
 				  bool supports_spill);
-void ac_shader_binary_clean(struct ac_shader_binary *b);
 
 #endif /* AC_BINARY_H */

src/amd/common/ac_debug.c

@@ -19,6 +19,9 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Marek Olšák <maraeo@gmail.com>
  */
 
 #include "ac_debug.h"

src/amd/common/ac_debug.h

@@ -19,8 +19,10 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Marek Olšák <maraeo@gmail.com>
  */
-
 #ifndef AC_DEBUG_H
 #define AC_DEBUG_H
 

src/amd/common/ac_gpu_info.c

@@ -98,9 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 {
 	struct amdgpu_buffer_size_alignments alignment_info = {};
 	struct amdgpu_heap_info vram, vram_vis, gtt;
-	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-	struct drm_amdgpu_info_hw_ip vce = {}, vcn_dec = {};
-	struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
+	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {};
 	uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
 	int r, i, j;
 	drmDevicePtr devinfo;
@@ -156,12 +154,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		return false;
 	}
 
-	r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
-	if (r) {
-		fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
-		return false;
-	}
-
 	r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
 	if (r) {
 		fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
@@ -182,14 +174,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		}
 	}
 
-	if (info->drm_major == 3 && info->drm_minor >= 17) {
-		r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
-		if (r) {
-			fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
-			return false;
-		}
-	}
-
 	r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 					&info->me_fw_version,
 					&info->me_fw_feature);
@@ -239,7 +223,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->vce_harvest_config = amdinfo->vce_harvest_config;
 
 	switch (info->pci_id) {
-#define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
+#define CHIPSET(pci_id, name, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
 #include "pci_ids/radeonsi_pci_ids.h"
 #undef CHIPSET
 
@@ -285,8 +269,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		vce.available_rings ? vce_version : 0;
 	info->has_userptr = true;
 	info->has_syncobj = has_syncobj(fd);
-	info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
-	info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
+	info->has_sync_file = info->has_syncobj && info->drm_minor >= 21;
 	info->has_ctx_priority = info->drm_minor >= 22;
 	info->num_render_backends = amdinfo->rb_pipes;
 	info->clock_crystal_freq = amdinfo->gpu_counter_freq;
@@ -332,16 +315,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	if (info->chip_class == SI)
 		info->gfx_ib_pad_with_type2 = TRUE;
 
-	unsigned ib_align = 0;
-	ib_align = MAX2(ib_align, gfx.ib_start_alignment);
-	ib_align = MAX2(ib_align, compute.ib_start_alignment);
-	ib_align = MAX2(ib_align, dma.ib_start_alignment);
-	ib_align = MAX2(ib_align, uvd.ib_start_alignment);
-	ib_align = MAX2(ib_align, vce.ib_start_alignment);
-	ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
-	ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
-	info->ib_start_alignment = ib_align;
-
 	return true;
 }
 
@@ -372,58 +345,3 @@ void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
 	uint_uuid[2] = info->pci_dev;
 	uint_uuid[3] = info->pci_func;
 }
-
-void ac_print_gpu_info(struct radeon_info *info)
-{
-	printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
-	       info->pci_domain, info->pci_bus,
-	       info->pci_dev, info->pci_func);
-	printf("pci_id = 0x%x\n", info->pci_id);
-	printf("family = %i\n", info->family);
-	printf("chip_class = %i\n", info->chip_class);
-	printf("pte_fragment_size = %u\n", info->pte_fragment_size);
-	printf("gart_page_size = %u\n", info->gart_page_size);
-	printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
-	printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
-	printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
-	printf("max_alloc_size = %i MB\n",
-	       (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
-	printf("min_alloc_size = %u\n", info->min_alloc_size);
-	printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
-	printf("has_virtual_memory = %i\n", info->has_virtual_memory);
-	printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
-	printf("has_hw_decode = %u\n", info->has_hw_decode);
-	printf("num_sdma_rings = %i\n", info->num_sdma_rings);
-	printf("num_compute_rings = %u\n", info->num_compute_rings);
-	printf("uvd_fw_version = %u\n", info->uvd_fw_version);
-	printf("vce_fw_version = %u\n", info->vce_fw_version);
-	printf("me_fw_version = %i\n", info->me_fw_version);
-	printf("me_fw_feature = %i\n", info->me_fw_feature);
-	printf("pfp_fw_version = %i\n", info->pfp_fw_version);
-	printf("pfp_fw_feature = %i\n", info->pfp_fw_feature);
-	printf("ce_fw_version = %i\n", info->ce_fw_version);
-	printf("ce_fw_feature = %i\n", info->ce_fw_feature);
-	printf("vce_harvest_config = %i\n", info->vce_harvest_config);
-	printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
-	printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
-	printf("drm = %i.%i.%i\n", info->drm_major,
-	       info->drm_minor, info->drm_patchlevel);
-	printf("has_userptr = %i\n", info->has_userptr);
-	printf("has_syncobj = %u\n", info->has_syncobj);
-	printf("has_fence_to_handle = %u\n", info->has_fence_to_handle);
-
-	printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes);
-	printf("max_shader_clock = %i\n", info->max_shader_clock);
-	printf("num_good_compute_units = %i\n", info->num_good_compute_units);
-	printf("max_se = %i\n", info->max_se);
-	printf("max_sh_per_se = %i\n", info->max_sh_per_se);
-
-	printf("r600_gb_backend_map = %i\n", info->r600_gb_backend_map);
-	printf("r600_gb_backend_map_valid = %i\n", info->r600_gb_backend_map_valid);
-	printf("r600_num_banks = %i\n", info->r600_num_banks);
-	printf("num_render_backends = %i\n", info->num_render_backends);
-	printf("num_tile_pipes = %i\n", info->num_tile_pipes);
-	printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
-	printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
-	printf("max_alignment = %u\n", (unsigned)info->max_alignment);
-}

src/amd/common/ac_gpu_info.h

@@ -61,7 +61,6 @@ struct radeon_info {
 	bool                        has_virtual_memory;
 	bool                        gfx_ib_pad_with_type2;
 	bool                        has_hw_decode;
-	unsigned                    ib_start_alignment;
 	uint32_t                    num_sdma_rings;
 	uint32_t                    num_compute_rings;
 	uint32_t                    uvd_fw_version;
@@ -82,8 +81,7 @@ struct radeon_info {
 	uint32_t                    drm_patchlevel;
 	bool                        has_userptr;
 	bool                        has_syncobj;
-	bool                        has_syncobj_wait_for_submit;
-	bool                        has_fence_to_handle;
+	bool                        has_sync_file;
 	bool                        has_ctx_priority;
 
 	/* Shader cores. */
@@ -117,7 +115,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 void ac_compute_driver_uuid(char *uuid, size_t size);
 
 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
-void ac_print_gpu_info(struct radeon_info *info);
 
 #ifdef __cplusplus
 }

src/amd/common/ac_llvm_build.c

@@ -41,28 +41,17 @@
 
 #include "shader_enums.h"
 
-#define AC_LLVM_INITIAL_CF_DEPTH 4
-
-/* Data for if/else/endif and bgnloop/endloop control flow structures.
- */
-struct ac_llvm_flow {
-	/* Loop exit or next part of if/else/endif. */
-	LLVMBasicBlockRef next_block;
-	LLVMBasicBlockRef loop_entry_block;
-};
-
 /* Initialize module-independent parts of the context.
  *
  * The caller is responsible for initializing ctx::module and ctx::builder.
  */
 void
 ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
-		     enum chip_class chip_class, enum radeon_family family)
+		     enum chip_class chip_class)
 {
 	LLVMValueRef args[1];
 
 	ctx->chip_class = chip_class;
-	ctx->family = family;
 
 	ctx->context = context;
 	ctx->module = NULL;
@@ -77,24 +66,14 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
 	ctx->f16 = LLVMHalfTypeInContext(ctx->context);
 	ctx->f32 = LLVMFloatTypeInContext(ctx->context);
 	ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
-	ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
-	ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
 	ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
-	ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
 	ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
 	ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
 
 	ctx->i32_0 = LLVMConstInt(ctx->i32, 0, false);
 	ctx->i32_1 = LLVMConstInt(ctx->i32, 1, false);
-	ctx->i64_0 = LLVMConstInt(ctx->i64, 0, false);
-	ctx->i64_1 = LLVMConstInt(ctx->i64, 1, false);
 	ctx->f32_0 = LLVMConstReal(ctx->f32, 0.0);
 	ctx->f32_1 = LLVMConstReal(ctx->f32, 1.0);
-	ctx->f64_0 = LLVMConstReal(ctx->f64, 0.0);
-	ctx->f64_1 = LLVMConstReal(ctx->f64, 1.0);
-
-	ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
-	ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
 
 	ctx->range_md_kind = LLVMGetMDKindIDInContext(ctx->context,
 						     "range", 5);
@@ -113,38 +92,6 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
 	ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
 }
 
-void
-ac_llvm_context_dispose(struct ac_llvm_context *ctx)
-{
-	free(ctx->flow);
-	ctx->flow = NULL;
-	ctx->flow_depth_max = 0;
-}
-
-int
-ac_get_llvm_num_components(LLVMValueRef value)
-{
-	LLVMTypeRef type = LLVMTypeOf(value);
-	unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
-	                              ? LLVMGetVectorSize(type)
-	                              : 1;
-	return num_components;
-}
-
-LLVMValueRef
-ac_llvm_extract_elem(struct ac_llvm_context *ac,
-		     LLVMValueRef value,
-		     int index)
-{
-	if (LLVMGetTypeKind(LLVMTypeOf(value)) != LLVMVectorTypeKind) {
-		assert(index == 0);
-		return value;
-	}
-
-	return LLVMBuildExtractElement(ac->builder, value,
-				       LLVMConstInt(ac->i32, index, false), "");
-}
-
 unsigned
 ac_get_type_size(LLVMTypeRef type)
 {
@@ -417,28 +364,6 @@ ac_build_vote_eq(struct ac_llvm_context *ctx, LLVMValueRef value)
 	return LLVMBuildOr(ctx->builder, all, none, "");
 }
 
-LLVMValueRef
-ac_build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
-			       unsigned value_count, unsigned component)
-{
-	LLVMValueRef vec = NULL;
-
-	if (value_count == 1) {
-		return values[component];
-	} else if (!value_count)
-		unreachable("value_count is 0");
-
-	for (unsigned i = component; i < value_count + component; i++) {
-		LLVMValueRef value = values[i];
-
-		if (i == component)
-			vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), value_count));
-		LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, false);
-		vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, "");
-	}
-	return vec;
-}
-
 LLVMValueRef
 ac_build_gather_values_extended(struct ac_llvm_context *ctx,
 				LLVMValueRef *values,
@@ -486,7 +411,6 @@ ac_build_fdiv(struct ac_llvm_context *ctx,
 {
 	LLVMValueRef ret = LLVMBuildFDiv(ctx->builder, num, den, "");
 
-	/* Use v_rcp_f32 instead of precise division. */
 	if (!LLVMIsConstant(ret))
 		LLVMSetMetadata(ret, ctx->fpmath_md_kind, ctx->fpmath_md_2p5_ulp);
 	return ret;
@@ -1005,7 +929,11 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
 
 	return ac_build_intrinsic(ctx, name, types[func], args,
 				  ARRAY_SIZE(args),
-				  ac_get_load_intr_attribs(can_speculate));
+				  /* READNONE means writes can't affect it, while
+				   * READONLY means that writes can affect it. */
+				  can_speculate && HAVE_LLVM >= 0x0400 ?
+					  AC_FUNC_ATTR_READNONE :
+					  AC_FUNC_ATTR_READONLY);
 }
 
 LLVMValueRef ac_build_buffer_load_format(struct ac_llvm_context *ctx,
@@ -1018,34 +946,18 @@ LLVMValueRef ac_build_buffer_load_format(struct ac_llvm_context *ctx,
 		LLVMBuildBitCast(ctx->builder, rsrc, ctx->v4i32, ""),
 		vindex,
 		voffset,
-		ctx->i1false, /* glc */
-		ctx->i1false, /* slc */
+		LLVMConstInt(ctx->i1, 0, 0), /* glc */
+		LLVMConstInt(ctx->i1, 0, 0), /* slc */
 	};
 
 	return ac_build_intrinsic(ctx,
 				  "llvm.amdgcn.buffer.load.format.v4f32",
 				  ctx->v4f32, args, ARRAY_SIZE(args),
-				  ac_get_load_intr_attribs(can_speculate));
-}
-
-LLVMValueRef ac_build_buffer_load_format_gfx9_safe(struct ac_llvm_context *ctx,
-                                                  LLVMValueRef rsrc,
-                                                  LLVMValueRef vindex,
-                                                  LLVMValueRef voffset,
-                                                  bool can_speculate)
-{
-	LLVMValueRef elem_count = LLVMBuildExtractElement(ctx->builder, rsrc, LLVMConstInt(ctx->i32, 2, 0), "");
-	LLVMValueRef stride = LLVMBuildExtractElement(ctx->builder, rsrc, LLVMConstInt(ctx->i32, 1, 0), "");
-	stride = LLVMBuildLShr(ctx->builder, stride, LLVMConstInt(ctx->i32, 16, 0), "");
-
-	LLVMValueRef new_elem_count = LLVMBuildSelect(ctx->builder,
-	                                              LLVMBuildICmp(ctx->builder, LLVMIntUGT, elem_count, stride, ""),
-	                                              elem_count, stride, "");
-
-	LLVMValueRef new_rsrc = LLVMBuildInsertElement(ctx->builder, rsrc, new_elem_count,
-	                                               LLVMConstInt(ctx->i32, 2, 0), "");
-
-	return ac_build_buffer_load_format(ctx, new_rsrc, vindex, voffset, can_speculate);
+				  /* READNONE means writes can't affect it, while
+				   * READONLY means that writes can affect it. */
+				  can_speculate && HAVE_LLVM >= 0x0400 ?
+					  AC_FUNC_ATTR_READNONE :
+					  AC_FUNC_ATTR_READONLY);
 }
 
 /**
@@ -1238,7 +1150,7 @@ ac_build_umsb(struct ac_llvm_context *ctx,
 {
 	LLVMValueRef args[2] = {
 		arg,
-		ctx->i1true,
+		LLVMConstInt(ctx->i1, 1, 0),
 	};
 	LLVMValueRef msb = ac_build_intrinsic(ctx, "llvm.ctlz.i32",
 					      dst_type, args, ARRAY_SIZE(args),
@@ -1256,22 +1168,6 @@ ac_build_umsb(struct ac_llvm_context *ctx,
 			       LLVMConstInt(ctx->i32, -1, true), msb, "");
 }
 
-LLVMValueRef ac_build_fmin(struct ac_llvm_context *ctx, LLVMValueRef a,
-			   LLVMValueRef b)
-{
-	LLVMValueRef args[2] = {a, b};
-	return ac_build_intrinsic(ctx, "llvm.minnum.f32", ctx->f32, args, 2,
-				  AC_FUNC_ATTR_READNONE);
-}
-
-LLVMValueRef ac_build_fmax(struct ac_llvm_context *ctx, LLVMValueRef a,
-			   LLVMValueRef b)
-{
-	LLVMValueRef args[2] = {a, b};
-	return ac_build_intrinsic(ctx, "llvm.maxnum.f32", ctx->f32, args, 2,
-				  AC_FUNC_ATTR_READNONE);
-}
-
 LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a,
 			   LLVMValueRef b)
 {
@@ -1282,8 +1178,20 @@ LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a,
 LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value)
 {
 	if (HAVE_LLVM >= 0x0500) {
-		return ac_build_fmin(ctx, ac_build_fmax(ctx, value, ctx->f32_0),
-				     ctx->f32_1);
+		LLVMValueRef max[2] = {
+			value,
+			LLVMConstReal(ctx->f32, 0),
+		};
+		LLVMValueRef min[2] = {
+			LLVMConstReal(ctx->f32, 1),
+		};
+
+		min[1] = ac_build_intrinsic(ctx, "llvm.maxnum.f32",
+					    ctx->f32, max, 2,
+					    AC_FUNC_ATTR_READNONE);
+		return ac_build_intrinsic(ctx, "llvm.minnum.f32",
+					  ctx->f32, min, 2,
+					  AC_FUNC_ATTR_READNONE);
 	}
 
 	LLVMValueRef args[3] = {
@@ -1349,7 +1257,7 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
 	LLVMTypeRef dst_type;
 	LLVMValueRef args[11];
 	unsigned num_args = 0;
-	const char *name = NULL;
+	const char *name;
 	char intr_name[128], type[64];
 
 	if (HAVE_LLVM >= 0x0400) {
@@ -1368,9 +1276,9 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
 		args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
 		if (sample)
 			args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
-		args[num_args++] = ctx->i1false; /* glc */
-		args[num_args++] = ctx->i1false; /* slc */
-		args[num_args++] = ctx->i1false; /* lwe */
+		args[num_args++] = LLVMConstInt(ctx->i1, 0, 0); /* glc */
+		args[num_args++] = LLVMConstInt(ctx->i1, 0, 0); /* slc */
+		args[num_args++] = LLVMConstInt(ctx->i1, 0, 0); /* lwe */
 		args[num_args++] = LLVMConstInt(ctx->i1, a->da, 0);
 
 		switch (a->opcode) {
@@ -1497,26 +1405,20 @@ LLVMValueRef ac_build_cvt_pkrtz_f16(struct ac_llvm_context *ctx,
 				  AC_FUNC_ATTR_LEGACY);
 }
 
-LLVMValueRef ac_build_wqm_vote(struct ac_llvm_context *ctx, LLVMValueRef i1)
+/**
+ * KILL, AKA discard in GLSL.
+ *
+ * \param value  kill if value < 0.0 or value == NULL.
+ */
+void ac_build_kill(struct ac_llvm_context *ctx, LLVMValueRef value)
 {
-	assert(HAVE_LLVM >= 0x0600);
-	return ac_build_intrinsic(ctx, "llvm.amdgcn.wqm.vote", ctx->i1,
-				  &i1, 1, AC_FUNC_ATTR_READNONE);
-}
-
-void ac_build_kill_if_false(struct ac_llvm_context *ctx, LLVMValueRef i1)
-{
-	if (HAVE_LLVM >= 0x0600) {
-		ac_build_intrinsic(ctx, "llvm.amdgcn.kill", ctx->voidt,
-				   &i1, 1, 0);
-		return;
+	if (value) {
+		ac_build_intrinsic(ctx, "llvm.AMDGPU.kill", ctx->voidt,
+				   &value, 1, AC_FUNC_ATTR_LEGACY);
+	} else {
+		ac_build_intrinsic(ctx, "llvm.AMDGPU.kilp", ctx->voidt,
+				   NULL, 0, AC_FUNC_ATTR_LEGACY);
 	}
-
-	LLVMValueRef value = LLVMBuildSelect(ctx->builder, i1,
-					     LLVMConstReal(ctx->f32, 1),
-					     LLVMConstReal(ctx->f32, -1), "");
-	ac_build_intrinsic(ctx, "llvm.AMDGPU.kill", ctx->voidt,
-			   &value, 1, AC_FUNC_ATTR_LEGACY);
 }
 
 LLVMValueRef ac_build_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
@@ -1545,15 +1447,6 @@ LLVMValueRef ac_build_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
 				  AC_FUNC_ATTR_LEGACY);
 }
 
-void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned simm16)
-{
-	LLVMValueRef args[1] = {
-		LLVMConstInt(ctx->i32, simm16, false),
-	};
-	ac_build_intrinsic(ctx, "llvm.amdgcn.s.waitcnt",
-			   ctx->voidt, args, 1, 0);
-}
-
 void ac_get_image_intr_name(const char *base_name,
 			    LLVMTypeRef data_type,
 			    LLVMTypeRef coords_type,
@@ -1849,228 +1742,3 @@ void ac_init_exec_full_mask(struct ac_llvm_context *ctx)
 			   "llvm.amdgcn.init.exec", ctx->voidt,
 			   &full_mask, 1, AC_FUNC_ATTR_CONVERGENT);
 }
-
-void ac_declare_lds_as_pointer(struct ac_llvm_context *ctx)
-{
-	unsigned lds_size = ctx->chip_class >= CIK ? 65536 : 32768;
-	ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32_0,
-				     LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), AC_LOCAL_ADDR_SPACE),
-				     "lds");
-}
-
-LLVMValueRef ac_lds_load(struct ac_llvm_context *ctx,
-			 LLVMValueRef dw_addr)
-{
-	return ac_build_load(ctx, ctx->lds, dw_addr);
-}
-
-void ac_lds_store(struct ac_llvm_context *ctx,
-		  LLVMValueRef dw_addr,
-		  LLVMValueRef value)
-{
-	value = ac_to_integer(ctx, value);
-	ac_build_indexed_store(ctx, ctx->lds,
-			       dw_addr, value);
-}
-
-LLVMValueRef ac_find_lsb(struct ac_llvm_context *ctx,
-			 LLVMTypeRef dst_type,
-			 LLVMValueRef src0)
-{
-	LLVMValueRef params[2] = {
-		src0,
-
-		/* The value of 1 means that ffs(x=0) = undef, so LLVM won't
-		 * add special code to check for x=0. The reason is that
-		 * the LLVM behavior for x=0 is different from what we
-		 * need here. However, LLVM also assumes that ffs(x) is
-		 * in [0, 31], but GLSL expects that ffs(0) = -1, so
-		 * a conditional assignment to handle 0 is still required.
-		 *
-		 * The hardware already implements the correct behavior.
-		 */
-		LLVMConstInt(ctx->i1, 1, false),
-	};
-
-	LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
-					      params, 2,
-					      AC_FUNC_ATTR_READNONE);
-
-	/* TODO: We need an intrinsic to skip this conditional. */
-	/* Check for zero: */
-	return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
-							   LLVMIntEQ, src0,
-							   ctx->i32_0, ""),
-			       LLVMConstInt(ctx->i32, -1, 0), lsb, "");
-}
-
-static struct ac_llvm_flow *
-get_current_flow(struct ac_llvm_context *ctx)
-{
-	if (ctx->flow_depth > 0)
-		return &ctx->flow[ctx->flow_depth - 1];
-	return NULL;
-}
-
-static struct ac_llvm_flow *
-get_innermost_loop(struct ac_llvm_context *ctx)
-{
-	for (unsigned i = ctx->flow_depth; i > 0; --i) {
-		if (ctx->flow[i - 1].loop_entry_block)
-			return &ctx->flow[i - 1];
-	}
-	return NULL;
-}
-
-static struct ac_llvm_flow *
-push_flow(struct ac_llvm_context *ctx)
-{
-	struct ac_llvm_flow *flow;
-
-	if (ctx->flow_depth >= ctx->flow_depth_max) {
-		unsigned new_max = MAX2(ctx->flow_depth << 1,
-					AC_LLVM_INITIAL_CF_DEPTH);
-
-		ctx->flow = realloc(ctx->flow, new_max * sizeof(*ctx->flow));
-		ctx->flow_depth_max = new_max;
-	}
-
-	flow = &ctx->flow[ctx->flow_depth];
-	ctx->flow_depth++;
-
-	flow->next_block = NULL;
-	flow->loop_entry_block = NULL;
-	return flow;
-}
-
-static void set_basicblock_name(LLVMBasicBlockRef bb, const char *base,
-				int label_id)
-{
-	char buf[32];
-	snprintf(buf, sizeof(buf), "%s%d", base, label_id);
-	LLVMSetValueName(LLVMBasicBlockAsValue(bb), buf);
-}
-
-/* Append a basic block at the level of the parent flow.
- */
-static LLVMBasicBlockRef append_basic_block(struct ac_llvm_context *ctx,
-					    const char *name)
-{
-	assert(ctx->flow_depth >= 1);
-
-	if (ctx->flow_depth >= 2) {
-		struct ac_llvm_flow *flow = &ctx->flow[ctx->flow_depth - 2];
-
-		return LLVMInsertBasicBlockInContext(ctx->context,
-						     flow->next_block, name);
-	}
-
-	LLVMValueRef main_fn =
-		LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->builder));
-	return LLVMAppendBasicBlockInContext(ctx->context, main_fn, name);
-}
-
-/* Emit a branch to the given default target for the current block if
- * applicable -- that is, if the current block does not already contain a
- * branch from a break or continue.
- */
-static void emit_default_branch(LLVMBuilderRef builder,
-				LLVMBasicBlockRef target)
-{
-	if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(builder)))
-		 LLVMBuildBr(builder, target);
-}
-
-void ac_build_bgnloop(struct ac_llvm_context *ctx, int label_id)
-{
-	struct ac_llvm_flow *flow = push_flow(ctx);
-	flow->loop_entry_block = append_basic_block(ctx, "LOOP");
-	flow->next_block = append_basic_block(ctx, "ENDLOOP");
-	set_basicblock_name(flow->loop_entry_block, "loop", label_id);
-	LLVMBuildBr(ctx->builder, flow->loop_entry_block);
-	LLVMPositionBuilderAtEnd(ctx->builder, flow->loop_entry_block);
-}
-
-void ac_build_break(struct ac_llvm_context *ctx)
-{
-	struct ac_llvm_flow *flow = get_innermost_loop(ctx);
-	LLVMBuildBr(ctx->builder, flow->next_block);
-}
-
-void ac_build_continue(struct ac_llvm_context *ctx)
-{
-	struct ac_llvm_flow *flow = get_innermost_loop(ctx);
-	LLVMBuildBr(ctx->builder, flow->loop_entry_block);
-}
-
-void ac_build_else(struct ac_llvm_context *ctx, int label_id)
-{
-	struct ac_llvm_flow *current_branch = get_current_flow(ctx);
-	LLVMBasicBlockRef endif_block;
-
-	assert(!current_branch->loop_entry_block);
-
-	endif_block = append_basic_block(ctx, "ENDIF");
-	emit_default_branch(ctx->builder, endif_block);
-
-	LLVMPositionBuilderAtEnd(ctx->builder, current_branch->next_block);
-	set_basicblock_name(current_branch->next_block, "else", label_id);
-
-	current_branch->next_block = endif_block;
-}
-
-void ac_build_endif(struct ac_llvm_context *ctx, int label_id)
-{
-	struct ac_llvm_flow *current_branch = get_current_flow(ctx);
-
-	assert(!current_branch->loop_entry_block);
-
-	emit_default_branch(ctx->builder, current_branch->next_block);
-	LLVMPositionBuilderAtEnd(ctx->builder, current_branch->next_block);
-	set_basicblock_name(current_branch->next_block, "endif", label_id);
-
-	ctx->flow_depth--;
-}
-
-void ac_build_endloop(struct ac_llvm_context *ctx, int label_id)
-{
-	struct ac_llvm_flow *current_loop = get_current_flow(ctx);
-
-	assert(current_loop->loop_entry_block);
-
-	emit_default_branch(ctx->builder, current_loop->loop_entry_block);
-
-	LLVMPositionBuilderAtEnd(ctx->builder, current_loop->next_block);
-	set_basicblock_name(current_loop->next_block, "endloop", label_id);
-	ctx->flow_depth--;
-}
-
-static void if_cond_emit(struct ac_llvm_context *ctx, LLVMValueRef cond,
-			 int label_id)
-{
-	struct ac_llvm_flow *flow = push_flow(ctx);
-	LLVMBasicBlockRef if_block;
-
-	if_block = append_basic_block(ctx, "IF");
-	flow->next_block = append_basic_block(ctx, "ELSE");
-	set_basicblock_name(if_block, "if", label_id);
-	LLVMBuildCondBr(ctx->builder, cond, if_block, flow->next_block);
-	LLVMPositionBuilderAtEnd(ctx->builder, if_block);
-}
-
-void ac_build_if(struct ac_llvm_context *ctx, LLVMValueRef value,
-		 int label_id)
-{
-	LLVMValueRef cond = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
-					  value, ctx->f32_0, "");
-	if_cond_emit(ctx, cond, label_id);
-}
-
-void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
-		  int label_id)
-{
-	LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
-					  ac_to_integer(ctx, value),
-					  ctx->i32_0, "");
-	if_cond_emit(ctx, cond, label_id);
-}

src/amd/common/ac_llvm_build.h

@@ -34,12 +34,6 @@
 extern "C" {
 #endif
 
-enum {
-	AC_LOCAL_ADDR_SPACE = 3,
-};
-
-struct ac_llvm_flow;
-
 struct ac_llvm_context {
 	LLVMContextRef context;
 	LLVMModuleRef module;
@@ -54,27 +48,14 @@ struct ac_llvm_context {
 	LLVMTypeRef f16;
 	LLVMTypeRef f32;
 	LLVMTypeRef f64;
-	LLVMTypeRef v2i32;
-	LLVMTypeRef v3i32;
 	LLVMTypeRef v4i32;
-	LLVMTypeRef v2f32;
 	LLVMTypeRef v4f32;
 	LLVMTypeRef v8i32;
 
 	LLVMValueRef i32_0;
 	LLVMValueRef i32_1;
-	LLVMValueRef i64_0;
-	LLVMValueRef i64_1;
 	LLVMValueRef f32_0;
 	LLVMValueRef f32_1;
-	LLVMValueRef f64_0;
-	LLVMValueRef f64_1;
-	LLVMValueRef i1true;
-	LLVMValueRef i1false;
-
-	struct ac_llvm_flow *flow;
-	unsigned flow_depth;
-	unsigned flow_depth_max;
 
 	unsigned range_md_kind;
 	unsigned invariant_load_md_kind;
@@ -84,25 +65,11 @@ struct ac_llvm_context {
 	LLVMValueRef empty_md;
 
 	enum chip_class chip_class;
-	enum radeon_family family;
-
-	LLVMValueRef lds;
 };
 
 void
 ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
-		     enum chip_class chip_class, enum radeon_family family);
-
-void
-ac_llvm_context_dispose(struct ac_llvm_context *ctx);
-
-int
-ac_get_llvm_num_components(LLVMValueRef value);
-
-LLVMValueRef
-ac_llvm_extract_elem(struct ac_llvm_context *ac,
-		     LLVMValueRef value,
-		     int index);
+		     enum chip_class chip_class);
 
 unsigned ac_get_type_size(LLVMTypeRef type);
 
@@ -134,10 +101,6 @@ LLVMValueRef ac_build_vote_any(struct ac_llvm_context *ctx, LLVMValueRef value);
 
 LLVMValueRef ac_build_vote_eq(struct ac_llvm_context *ctx, LLVMValueRef value);
 
-LLVMValueRef
-ac_build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
-			       unsigned value_count, unsigned component);
-
 LLVMValueRef
 ac_build_gather_values_extended(struct ac_llvm_context *ctx,
 				LLVMValueRef *values,
@@ -225,14 +188,6 @@ LLVMValueRef ac_build_buffer_load_format(struct ac_llvm_context *ctx,
 					 LLVMValueRef voffset,
 					 bool can_speculate);
 
-/* load_format that handles the stride & element count better if idxen is
- * disabled by LLVM. */
-LLVMValueRef ac_build_buffer_load_format_gfx9_safe(struct ac_llvm_context *ctx,
-                                                  LLVMValueRef rsrc,
-                                                  LLVMValueRef vindex,
-                                                  LLVMValueRef voffset,
-                                                  bool can_speculate);
-
 LLVMValueRef
 ac_get_thread_id(struct ac_llvm_context *ctx);
 
@@ -265,10 +220,7 @@ LLVMValueRef ac_build_imsb(struct ac_llvm_context *ctx,
 LLVMValueRef ac_build_umsb(struct ac_llvm_context *ctx,
 			  LLVMValueRef arg,
 			  LLVMTypeRef dst_type);
-LLVMValueRef ac_build_fmin(struct ac_llvm_context *ctx, LLVMValueRef a,
-			   LLVMValueRef b);
-LLVMValueRef ac_build_fmax(struct ac_llvm_context *ctx, LLVMValueRef a,
-			   LLVMValueRef b);
+
 LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a, LLVMValueRef b);
 LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value);
 
@@ -313,14 +265,11 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
 				   struct ac_image_args *a);
 LLVMValueRef ac_build_cvt_pkrtz_f16(struct ac_llvm_context *ctx,
 				    LLVMValueRef args[2]);
-LLVMValueRef ac_build_wqm_vote(struct ac_llvm_context *ctx, LLVMValueRef i1);
-void ac_build_kill_if_false(struct ac_llvm_context *ctx, LLVMValueRef i1);
+void ac_build_kill(struct ac_llvm_context *ctx, LLVMValueRef value);
 LLVMValueRef ac_build_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
 			  LLVMValueRef offset, LLVMValueRef width,
 			  bool is_signed);
 
-void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned simm16);
-
 void ac_get_image_intr_name(const char *base_name,
 			    LLVMTypeRef data_type,
 			    LLVMTypeRef coords_type,
@@ -333,28 +282,6 @@ void ac_optimize_vs_outputs(struct ac_llvm_context *ac,
 			    uint32_t num_outputs,
 			    uint8_t *num_param_exports);
 void ac_init_exec_full_mask(struct ac_llvm_context *ctx);
-
-void ac_declare_lds_as_pointer(struct ac_llvm_context *ac);
-LLVMValueRef ac_lds_load(struct ac_llvm_context *ctx,
-			 LLVMValueRef dw_addr);
-void ac_lds_store(struct ac_llvm_context *ctx,
-		  LLVMValueRef dw_addr, LLVMValueRef value);
-
-LLVMValueRef ac_find_lsb(struct ac_llvm_context *ctx,
-			 LLVMTypeRef dst_type,
-			 LLVMValueRef src0);
-
-void ac_build_bgnloop(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_break(struct ac_llvm_context *ctx);
-void ac_build_continue(struct ac_llvm_context *ctx);
-void ac_build_else(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_endif(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_endloop(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_if(struct ac_llvm_context *ctx, LLVMValueRef value,
-		 int lable_id);
-void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
-		  int lable_id);
-
 #ifdef __cplusplus
 }
 #endif

src/amd/common/ac_llvm_helper.cpp

@@ -35,7 +35,6 @@
 #include <llvm/ExecutionEngine/ExecutionEngine.h>
 #include <llvm/IR/Attributes.h>
 #include <llvm/IR/CallSite.h>
-#include <llvm/IR/IRBuilder.h>
 
 #if HAVE_LLVM < 0x0500
 namespace llvm {
@@ -81,32 +80,3 @@ bool ac_llvm_is_function(LLVMValueRef v)
 	return llvm::isa<llvm::Function>(llvm::unwrap(v));
 #endif
 }
-
-LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
-				 enum ac_float_mode float_mode)
-{
-	LLVMBuilderRef builder = LLVMCreateBuilderInContext(ctx);
-
-#if HAVE_LLVM >= 0x0308
-	llvm::FastMathFlags flags;
-
-	switch (float_mode) {
-	case AC_FLOAT_MODE_DEFAULT:
-		break;
-	case AC_FLOAT_MODE_NO_SIGNED_ZEROS_FP_MATH:
-		flags.setNoSignedZeros();
-		llvm::unwrap(builder)->setFastMathFlags(flags);
-		break;
-	case AC_FLOAT_MODE_UNSAFE_FP_MATH:
-#if HAVE_LLVM >= 0x0600
-		flags.setFast();
-#else
-		flags.setUnsafeAlgebra();
-#endif
-		llvm::unwrap(builder)->setFastMathFlags(flags);
-		break;
-	}
-#endif
-
-	return builder;
-}